Inconsistency between the original CCS 3.3 and the CCS3.3 with the new SP12 and CGT

If this is a DSP/BIOS project, there might need to be coordination between the SR12 and CGT 6.1.5 and the latest BIOS release. Please confirm or verify this.

It is also possible that when updating the tools, some old paths might be specified in your .pjt project file. This is a text file that you can view and edit separately from CCS if there are any paths that should be updated to match the new CGT release.

Also, libraries that have already been included in your project might also need to be pulled in from the new updates, especially rts64plus.lib.

Thank you Randy

- My project is NOT a DSP/BIOS one

- What kind of text file are you talking about? Can you be more specific?

- Under the Libararies branch in the File View window of my project, there is no other libs inside. In the .cmd file of my project, there is following script

-l csl_c6455.lib
-l rts64plus.lib

Does this mean that I  have to update these two libs separately? Using the Update Advisor, where can I find the new dupates for these two libs? Or maybe there have been already some where and I should do something to let my project to use these new lib.

Thank you very much

Renaissance said:

- What kind of text file are you talking about? Can you be more specific?

An ASCII text file. You can edit it with a simple editor, like notepad.exe, but possibly not a document editor like Word. But if you are not comfortable with editing the file, you do not have to do that. See below.

Renaissance said:

- Under the Libararies branch in the File View window of my project, there is no other libs inside. In the .cmd file of my project, there is following script

-l csl_c6455.lib
-l rts64plus.lib

Some recommendations to try, since my concern is still that the wrong libraries are being picked up by the linker:

1. Comment the "-l rts64plus.lib" line as in /* -l rts64plus.lib */, and then rebuild the project. The linker may try to find the best compatible library.
2. Edit the "-l rts64plus.lib" line as in "-l C:\CCStudio_v3.3\C6000\cgt_6.1.5\lib\rts64plus.lib", and then rebuild the project. Be sure to use the correct path for your installation of the CGT files.
3. Comment the "-l rts64plus.lib" line as in /* -l rts64plus.lib */, and then use the Add Files to Project option to include this file from within the CGT 6.1.5 folder. Rebuild and test your application.

If none of this helps, you may want to re-post your problem to the Code Composer Studio IDE Sub-Forum.

Hi Randy:

Thank you for your suggestion. I tried the suggestions you made by specifying the new lib location in the .cmd file. Then I re-built the project. However, the running results based on this new .out are still wrong.

I want to re-post thsi problem to CCS sub-Forum. However, I could not locate the forum. Can you give me a link? (Are you talking about this forum??

TI Home > TI E2E Community (Beta) > Forums > Embedded Software and Tools > Code Composer  )

Thank you very much,

Renaissance

Yes, that is the right place to re-post.

Once you have made the new posting, please also post a link to it in this thread, like what you did above. That way I can easily follow the progress in the new location.

Please make sure the .cio section is being allocated, by the linker, to RAM, and not to flash, or some other form of memory which cannot be written during runtime.  This step is performed in a linker command file with syntax similar to:

.cio > RAM

Hope this helps ...

-George

Thank you George.

Here is the .cmd file of my project. You can see the .cio has been allocated in the L2

-c
-heap  0x1000
-stack 0x3000
-l csl_c6455.lib
//-l rts64plus.lib
-l C:\CCStudio_v3.3\C6000\cgt_6.1.5\lib\rts64plus.lib

/* Memory Map 1 - the default */
MEMORY
{     
     vecs:    o = 00000000h   l = 00000200h
        boot:    o = 00000200h   l = 00000200h 
     L1D:     o = 00f00000h   l = 00008000h
        L1P:     o = 00e00000h   l = 00008000h
        L2:      o = 00800000h   l = 00200000h
  DDR2:  o = 0e0000000h  l = 010000000h
}

SECTIONS
{
    .csl_vect   >       vecs
 .funct1     >       L2
 .funct2     >       L2
    .text       >       L2
    .stack      >       L2
    .bss        >       L2
    .cinit      >       L2
    .cio        >       L2
    .const      >       L2
    .data       >       L2
    .switch     >       L2
    .sysmem     >       L2
    .far        >       L2
    .testMem    >       L2 
    ISRAM       >       L2
 .chip_image >       L2
 .L1D_RAM >   L1D
 .ext_image  >       DDR2
}

Your link command file looks fine.  Do you have any reason to believe the memory location 0x9e8d80 cannot support random access?

Thanks and regards,

-George

I don't know.

THere is one thing about this error. It only happend when I  use the CCS 3.3 with the SR12 and the CGT6.1.5. When I use the original CCS3.3 without these update, the program is running without any problem..

I think your "vecs" section should be at the beginning of L2. Try moving it to the beginning of L2 and be sure to shift L2 up by 0200h. This is a long shot for being the error, but it is worth a try.

Since the complete path for the rts64plus.lib did not help, you can uncomment the commented line and delete the line after it with the complete path. This will have to be edited for the following step to work, anyway.

In Component Manager (Help->About [click Component Manager]), you can select the compiler release you want to use. Click the + by Build Tools, then TMS320C64XX, then select the original CGT, File->Save and File->Exit. Try this to see if it makes the program run again. If so, we need to understand why, because there are a lot of improvements to be gained by moving to the newer release.

Please look at your .map file and see what data memory is immediately before the .cio section. Is it possible that an errant pointer is allowing bad data to be written into the .cio section?

My theory ... Changing compiler tools in turn changed the position of .cio in memory.  This change in position exposes some other bug in the system that has been there all along.  To test this theory ...  First find the memory location of .cio in the working version by inspecting the map file from the working build.  Say .cio is at address 0x80abc0.  Next, temporarily change to allocation of the .cio section to

.cio > 0x80abc0

Then, build with v6.1.5.  See if that works.  If it does, then my theory, while not completely proven, seems pretty good.  The tools themselves are not the problem.  Changing the location of .cio is the problem.  It narrows the focus.

Hope this helps ...

-George

THank you George and Randy.

I just check the .map file of my project

(1) for the project I buit using the CCS3.3(SR12 and CGT 6.1.5) with optimization

 .......
                  009e54e4    00000004     --HOLE-- [fill = 0]
                  009e54e8    0000000c                   : fopen.obj (.cinit)
                  009e54f4    00000008     --HOLE-- [fill = 0]

.funct2    0    009e5500    00000140    
                  009e5500    00000140     sc2d.obj (.funct2)

.cio       0    009e5640    00000120     UNINITIALIZED
                  009e5640    00000120     rts64plus.lib : trgmsg.obj (.cio)
.......

.......
                  009e81fc    00000004     --HOLE-- [fill = 0]
                  009e8200    0000000c                   : fopen.obj (.cinit)
                  009e820c    00000008     --HOLE-- [fill = 0]

.funct2    0    009e8220    00000160    
                  009e8220    00000160     sc2d.obj (.funct2)

.cio       0    009e8380    00000120     UNINITIALIZED
                  009e8380    00000120     rts64plus.lib : trgmsg.obj (.cio)
.......

I can see the on/off of the optimization option did change the .cio location. So, I make another comparsion between the .map of the project buit using the CCS3.3(SR12 and CGT 6.1.5) with optimization and the .map of the project buit using the CCS3.3(WITHOUT SR12 and CGT 6.1.5) with optimization. In fact, those two .map files are exactly same. Now, the problem is why the running results are different based on these two build....

Hi,

With the same upgrade but using C6727 and code gen tools upgraded to ver 6.1.21, the i am getting the linker error that it cannot recognise int00 symbol. Thus linker is unablet to link.  I am using PADK with C6727 and CCS 3.3.82.

Please help as to what could be the error. All the settings are given correctly.

anushree