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Error detection on VLYNQ serial line protocol

Jack Sudarev
Prodigy 80 points

G'Day,

We are evaluating a possibility of using VLYNQ as a serial protocol between TI DSP and FPGA. The information on the actual VLYNQ physical serial line protocol implementation does not specify any checksum protection. The VLYNQ wires will be run between two different boards in fairly noisy conditions.

The question is whether there is any CRC or other mechanism to detect an error in the actual address and/or data fields of a VLYNQ packet.

Regards,

Jack.

  • 0
    TI__Guru* 84110 points

    VLYNQ is not intended for use in noisy conditions between boards. It is intended for communication between devices on a local board to provide a memory-like interface on the parallel side of the VLYNQ peripheral.

    The 8b/10b encoding is the only error support available in the hardware, but you can always add a CRC at the end of any block that you want to transfer. As you alluded, the addresses would not directly be helped by that.

    Your SRIO would give you a better inter-board communication link.

    Of course, nobody likes a noisy environment in electronics, so maybe that can be worked, too?