TDA4VM: J721S2 Dual Comparator Clock

Any thoughts?

Thanks for the information. The table was is taken from a fairly old version of the TRM (December 2020). I see looking at newer versions for both J721E and J721S2 these tables were removed. The section this was in was 12.11.1.2 DCC Integration.

Is see how the tables in clock mapping line up to the old version and can now move forward with testing.

Thanks!

Is this helpful?

This was very helpful. On additional oddity I see is that many of the CLKSRC's seem to have an additional /10 implemented for the DCC.

For instance, PLL26 HSDIV0 (DDR1) is set to 1066MHz. This lines up with DCC4, CLKSRC3 with a /4 divider which should be reading at 267MHz.

Testing this for the DCC ended up failing and checking the counts they were going down, but only about 10%. I then tested 26.7MHz and it passed. Is this expected? I am seeing this /10 on quite a few of the other CLKSRCs as well.

One additional question, I am testing the same thing above with the PLL12 HSDIV0 (DDR0) and the counts for the clksrc never start even though it is enabled as well. Any thoughts why this DCC clock may not be working?

I have only been testing in single shot mode so far.

David,

Try this (and I'm sorry that it wasn't clearer before):

1.) INPUT00, INPUT 01, and INPUT 02 are mapped  in register DCC_CLKSRC0 (0, 1, 2) as you would expect.

2.) INPUT10 is mapped as an input clock in register DCC_CLKSRC1 source 0; and this mapping is not at all clear and NOT as you might expect

3.) CLKSRC0 -- CLKSRC7 are clock inputs mapped by DCC_CLKSRC1 with a source +1 from their title; so CLKSRC0 is actually DCC_CLKSRC1, source 0+1; CLKSRC2 is mapped by DCC_CLKSRC1, source 2+1...

4) VBUSCLK can be mapped by DCC_CLKSRC1, source 9 and above.

If this is not clear enough, please follow-up.

Kevin

Thanks for the clarity, the test I thought I was running for DDR1 was running for DDR0 and now both are running as expected.

I am still seeing the divide by 10 on the DDR timing. Here is the read of DDR1 testing after completion with a success.

INPUT 02 is used as the reference and runs at 12.5MHz.
You can see the ratio of the two seed values is ( 1048575/( 466331 * ~1.05 (drift) ) ) = 2.14

12.5MHz * 2.14 = 26.7MHz.

I just tested with INPUT 00 which is at 19.2MHz and changed the frequency of the DDR clocks to 267000MHz and it works.

The frequency of INPUT 02 must be 125MHz then, but not totally sure that makes sense? INPUT 01 is also passing at 125MHz.

David,

The value of "5" in CLKSRC0 is confusing to me. I would have thought that you'd want it to be 0x2 if you were selecting the 12.5MHz internal oscillator.

Kevin

David,

Maybe a little fuller explanation -- I think when you have 0x5 for the DCC_CLKSRC0, you are selecting the VBUS_CLK. 

I tested this for DCC_CLKSRC0 = 0x3 and DCC_CLKSRC = 0x5; in both cases, the clock is coming from VBUS_CLK.

Kevin

Thanks Kevin, that answered it. I was still using the const variables from the example code which matches the CLKSRC0 (0) CLKSRC1 (0xA) CLKSRC2 (0x5) shown in the table 12-14577 that Brad posted above. I understand your comment earlier now better.