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boot problem on C6713

lei 14451
Prodigy 40 points

Other Parts Discussed in Thread: TPS3823

hello,

I have a boot problem on C6713,the boot is correct when I set a manual reset,but it's not correct when power on.The bootmode is configured as flash boot. The reset chip is TPS3823. I think that power on reset is same as the manual reset.What's the problem.

.

  • 0
    TI__Mastermind 18130 points

    Hi there,

    What exactly is the problem? Are you saying the board does not boot unless you manually reset after power up? Do you have the BOOTMODE pins pulled directly to ground or voltage or do you have another 'smart' device (FPGA, microcontroller) driving them? If the latter then make certain this device is driving them properly by the time the DSP is pulled out of reset.

    Otherwise it might be that the device is being pulled out of reset too quickly and the device hasn't had a chance to power up properly. Make certain that you are following the reset timing requirements per p121 of the 6713B datasheet.

  • 0 in reply to TimHarron
    Prodigy 40 points

    Thank you for your reply.

    I have not describe the problem clearly.The board does not boot unless I manually reset after power up. I confirm that the bootmode pins ,that is HD4 and HD3,are  01  on  the positive edge of the reset  signal and the width of the reset signal is 200 ms which is bigger than the requsted width. The HD4 pin is pulled to ground through a resistor.

    The data and address bus are buffered through the SN74LVC16245.The /OE pins of these 16245 are not enabled when the DSP is reset. 

  • 0 in reply to lei 14451
    TI__Guru* 84110 points

    Since the manual reset and the power-on reset are being applied by the same TPS3823 device to the same pin on the C6713, there is no electrical or logic difference between those.

    But something is different between the two cases. One thing to try that would be helpful is to hold the manual reset button down while turning on the power and wait a couple of seconds after the power has all come up before releasing the manual reset.

    If this test case allows the DSP to boot successfully, then the problem is that some conditions are not correct when the TPS3823 is ready to release the reset, even though it delays 200 ms. Perhaps another power rail is not ready or a clock or clock generator or PLL is not ready, yet. You can then either extend the delay for the POR (if possible) to allow for everything else to get ready, or you can start comparing every signal and voltage supply coming to the DSP to determine what is different at 200 ms vs. at 2000 ms.

    If this test case still does not let the DSP boot correctly, then pressing and releasing the button again does let the DSP boot, then I do not have any easy guesses. You will need to look at all of the vital signal and voltages during this time and try to figure out what is different when the manual reset is applied later.

  • 0 in reply to RandyP
    TI__Mastermind 18130 points

    lei said:
    The data and address bus are buffered through the SN74LVC16245.The /OE pins of these 16245 are not enabled when the DSP is reset. 

    Isn't this the problem? If the pins are expected to go through a buffer while the output enable is disabled, wouldn't this prevent any of the signals from the EMIF communicating with the external memory? When do the buffer's /OE pins get enabled? Also, this device has bus-hold features which I have seen cause issues in the past (usually with boot pins on the EMIF bus, but something to keep in mind).

  • 0 in reply to TimHarron
    Prodigy 40 points

    Thank you for reply.

    My DSP system is designed as a minumum system.It contains SDRAM,FLASH and it's necessary  accessory such as clock circuit and reset circuit. The SDRAM and FLASH are directly connected to the DSP's bus.

    The DSP system board is connected to another board through the DSP's expansion bus.The expansion is buffered by the chip 16245.so it has nothing with the DSP's boot.

  • 0 in reply to RandyP
    Prodigy 40 points

    thank you very much.

    I tried your test case and DSP booted successfully.Now I delay the reset signal 100ms,so the real reset signal is about 300ms and DSP boot successfully every time when power on .

    But I have not find  where the real problem is.Before I delay the reset signal,I checked the HD4 ，HD3  on the positive edge of the reset signal.It's right. I also checked the ECLKOUT,it has output.The DVDD and CVDD is also right .

    so where is the possible problem.