TDA4VM: How to set MIPI DSI to Non-Burst Mode with Sync Pulses.

hi wenyu chen,

did not get it, what is DSI output in non-burst mode? 

Regards,

Brijesh

HI,  Brijesh 
please check this file about MIPI DSI non-burst mode with sync pulse.

I want to set this mode.

thanks!

Hi wenyu chen,

I think by default DSI driver configures the output in this mode. I see this mode is selected by configuring timing parameters correctly. It seems driver uses the same equations for calculating timing parameters.. Is there anything specific that you are looking for in this mode? 

Regards,

Brijesh

HI, Brijesh:
Another question about DSS DSI output.

Camera DATA flow:  DSS=>ti941 (DSS DSI port)

file:vision_apps/platfrom/j721e/rtos/common/app_init.c

Use default size：data from DSS to TI941 are normal.  detected wave  are normal use Oscilloscope.

prm.display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_DSI;
prm.timings.width = 1280U;
prm.timings.height = 800U;
prm.timings.hFrontPorch = 110U;
prm.timings.hBackPorch = 220U;
prm.timings.hSyncLen = 40U;
prm.timings.vFrontPorch = 5U;
prm.timings.vBackPorch = 20U;
prm.timings.vSyncLen = 5U;
prm.timings.pixelClock = 74250000ULL;

Use our customer's size：data from DSS to TI941 are abnormal.  Oscilloscope can not detect wave from mipi data lane.

prm.display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_DSI;
prm.timings.width = 864U;
prm.timings.height = 480U;
prm.timings.hFrontPorch = 60U;
prm.timings.hBackPorch = 70U;
prm.timings.hSyncLen = 6U;
prm.timings.vFrontPorch = 35U;
prm.timings.vBackPorch = 9U;
prm.timings.vSyncLen = 1U;
prm.timings.pixelClock = 31500000ULL;

QA: How to config these parameters? any other parameters need to modify ?

    in file pdk_jacinto_08_01_00_33/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlDsi.c 

dsiObj->dphyTxIpDiv = 0x2;
dsiObj->dphyTxOpDiv = 0x2;
dsiObj->dphyTxFbDiv = 0x173;
dsiObj->dphyTxRate = 0x1CE;
dsiObj->cfgDsiTx.numOfLanes = 0x2u;
dsiObj->privDsiTx.numOfLanes = 0x2u;

how to modify these paramters?

Hi,

Please refer to below faq.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1019565/faq-processor-sdk-j721e-how-to-change-lane-speed-and-number-of-lanes-for-dsi-output

Regards,

Brijesh

HI, Brijesh:

I modify prm.timings.vSyncLen = 1U to prm.timings.vSyncLen = 5U,   TDA4 MIPI DSI output normally.

I found the  least value of  prm.timings.vSyncLen is 2U,  is there any document about how to set this parameter ?

thanks.

Hi wenyu chen,

I think vertical sync length requires to be more than 1, as vertical front porch is hard coded to be 1 in the driver and vfp should be less than vsync length for DSI output. 

Regards,

Brijesh 

HI, Brijesh:

I think vertical sync length requires to be more than 1, as vertical front porch is hard coded to be 1 in the driver and vfp should be less than vsync length for DSI output. 

========>I can't get your idea, please give more information， thanks！

Hi,

Please keep vSyncLen more than 1. 

Regards,

Brijesh