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DPLL4 clock settings in OMAP3530

Lakshmi Yeddula
Prodigy 30 points
Other Parts Discussed in Thread: OMAP3530

Hi all,

how can I configure DPLL4 in OMAP3530. In my design, it is configured to 864MHz, which is used as source clock for DSI PLL and PCLK. I need to configure PCLK to 74.25MHz to make use of HD feature. But with the current settings, PCLK is 72MHz. CM_CLKSEL2_PLL is the register in which we can set the multiplier and divider of DPLL4. But I need to know the formula or the source clock settings to produce the desired DPLL4 value.

 

Thanks,

Lakshmi.

  • 0
    Genius 5120 points

    Hi Lakshmi,

    I am referring OMAP3 TRM Dated SPRUF98I Revised on August 2010.

    To DPLL4 the input clock is SYS_CLK (Page number 305). You have to read the PRCM Chapter in the TRM.

    Long back ago I did some calculation. If I get I will respond here.

    Regards,

    GSR