TDA4VM: DDR at 4266 init failed

Hi 

    We do some boot test on our custom borad and find some DDR init failed when configured as 4266Mhz.

    SDK version is 07_03. DDR Chip is  MT53E1G32D2FW-046 AAT:B

    HW disign:

   DDR reg config file referring to e2e.ti.com/.../4094570

board_ddrRegInit.h

    We also do some changes in source file to analyse the failed log:

   for(counter = 0; counter < DDRSS_PLL_FHS_CNT; counter++)
    {
        /* wait for freq change request */
        regVal = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x80;
        BOARD_DEBUG_LOG("Reg Value: %d \n", regVal);

        while(regVal == 0x0)
        {
            regVal = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x80;
            BOARD_DEBUG_LOG("Reg Value: %d \n", regVal);
        }

        reqType = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x03;
        BOARD_DEBUG_LOG("Frequency Change type %d request from Controller \n", reqType);

        if(reqType == 1)
        {
            Board_DDRSetPLLClock(DDRSS_PLL_FREQUENCY_1);
            BOARD_DEBUG_LOG("#####Board_DDRSetPLLClock : %d \n", DDRSS_PLL_FREQUENCY_1);
        }
        else if(reqType == 2)
        {
            Board_DDRSetPLLClock(DDRSS_PLL_FREQUENCY_2);
            BOARD_DEBUG_LOG("#####Board_DDRSetPLLClock : %d \n", DDRSS_PLL_FREQUENCY_2);
        }
        else if(reqType == 0)
        {
#ifndef BOARD_DDR_ENABLE_PLL_BYPASS
            Board_DDRSetPLLExtBypass();
        // Board_DDRSetPLLClock(DDRSS_PLL_FREQUENCY_0);
            BOARD_DEBUG_LOG("#####Board_DDRSetPLLExtBypass 0##########\n");
#else
            Board_DDRSetPLLExtBypass();
            BOARD_DEBUG_LOG("#####Board_DDRSetPLLExtBypass 0##########\n");
#endif
        }

    Here is the log from mcu uart,the frequency of occurrence is almost 0.5 %

2022-10-09 22:55:35.191812  type 1 request from Controller ^M^M
#####Board_DDRSetPLLClock : 106
2022-10-09 22:55:35.256068 6500000 ^M^M
Reg Value: 0 ^M^M
Reg Value: 128 ^M^M
Frequency Change ty
2022-10-09 22:55:35.319700 pe 2 request from Controller ^M^M
#####Board_DDRSetPLLClock : 10665
2022-10-09 22:55:35.383598 00000 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Valu
2022-10-09 22:55:35.447636 e: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Valu
2022-10-09 22:55:35.511317 e: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Val
2022-10-09 22:55:35.575640 ue: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Val
2022-10-09 22:55:35.639197 ue: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Val
2022-10-09 22:55:35.703201 ue: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 0 ^M^M
Reg Value: 128 ^M^M
Frequ
2022-10-09 22:55:35.767094 ency Change type 1 request from Controller ^M^M
#####Board_DDRSetP
2022-10-09 22:55:35.830893 LLClock : 1066500000 ^M^M
Reg Value: 0 ^M^M
Reg Value: 128 ^M^M
Frequen
2022-10-09 22:55:35.894816 cy Change type 2 request from Controller ^M^M
#####Board_DDRSetPLLC
2022-10-09 22:55:35.958626 lock : 1066500000 ^M^M
--->>> Frequency Change request handshake is
2022-10-09 22:55:36.094621  completed... <<<---^M^M

2022-10-09 22:56:21.706586 Board_DDRStart: FAIL^M^M

   Is there any changes needed in config file? Or some changes in HW disign?