EVMC6472 + using cache

David,

I believe that BIOS5 has Cache Control built in.  You should just be able to do all of this from within your .tcf file and use the BCACHE APIs.  I don't know if the CSL APIs are compatible with Bios.

See the BCACHE module section of http://www.ti.com/litv/pdf/spru403r

Regards,

Dan

Hello RandyP

after implementing my code on evmc6472 using a single core, I am trying to implement it on multiple cores, that why I started with a simple example that looks like the c6472_Edma_IPC_BIOS project.

  This is the summary of my example, I have two tasks where the first is effected by the core2 and it permits to fill two buffers: BUF 1 and BUF2 and then send an IPC to core3 to begin the second task responsible for filling a third buffer buf3 then sending an IPC to core2  to edit another time the buf3.

  this example is just to know how can communicate between cores.

/*******************************************************************************************/

#define size 20
extern unsigned int SL2_Heap;
unsigned char *buf1;
unsigned char *buf2;
unsigned char *buf3;
void main()
{

.
.
//allocate three buffers in shared memory

buf1 = (unsigned char*)MEM_calloc(SL2_Heap, sizeof(unsigned char)*size, 8);
buf2 = (unsigned char*)MEM_calloc(SL2_Heap, sizeof(unsigned char)*size, 8); 
buf3 = (unsigned char*)MEM_calloc(SL2_Heap, sizeof(unsigned char)*size, 8);
IpcEventHook( 0, IPCIsr1 ); 
IpcEventHook( 1, IPCIsr2 );
.
.
}

void TSK_Stage1_fnc(void)
{
 int i;
    
 if ( CoreNum == 2 )
 {
  for(i=0;i<size;i++)
  {
   buf1[i]=2*i;
   buf2[i]=4*i;
   printf("buf1[%d] =%d  buf2[%d]=%d   \n",i,buf1[i],i,buf2[i]);
  }
  
  SetIpc( 3, 0 );  // send logical IPC to core 3
  
  SEM_pend( &SEM_Stage2, SYS_FOREVER );
  
  for(i=0;i<size;i++)
  {
   buf3[i]=buf3[i]>>1;
   printf("buf3[%d]=%d \n",i,buf3[i]);
  }
  for(i=0;i<size;i++)
 }
}
 
void TSK_Stage2_fnc(void)
{
 int i;
 SEM_pend( &SEM_Stage1, SYS_FOREVER );  // wait for signal to start, from last core sending 1st data
 if ( CoreNum == 3 )
 {
  for(i=0;i<size;i++)
  {
   buf3[i]=i;
   printf("buf3[%d]=%d \n",i,buf3[i]);
  }
  SetIpc( 2, 1 );  // send logical IPC to core 2
 } 
}
// ISR for the IPC interrupt for logical IPC1, posts SEM_Stage1
void IPCIsr1(void)
{
 SEM_post( &SEM_Stage1 );
}

// ISR for the IPC interrupt for logical IPC2, posts SEM_Stage2
void IPCIsr2(void)
{
 SEM_post( &SEM_Stage2 );
}

/*************************************************************************/

the problem I found is, when the core 3 sends an IPC to core 2, after calculating buf3, the Core 2 receives the IPC and normally it will make buf3 [i] = buf3 [i]>> 1;

  the problem was: the Core 2 did not use the new values ​​that are modified by core 3 in the task 2, but it uses the old values ​​which are zero although that all the three buffers are in shared memory.

  so how can I do to make the core 2 uses the new values ​​of buf3. and can you tell me if there are other problems in my example.

I will be very thankfull.

Cordialy

david
 

David,

Since this is marked Answered, you may not get many support views. If my answer is not sufficient, you may want to post this as a new thread. You can offer a link back to this thread if it makes it easier.

Cache coherency.

Set a breakpoint on each processor after the SEM_pend's, then look at the buffers in a memory window before and after the processing loops. Especially observe any color coding that shows values stored in cache. Then you may want to halt another processor and observe the same buffers from its point-of-view.

What do you find, or is this debug technique helpful at all?

Regards,
RandyP

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