c6205 pci !!!

Jianjie, here is what I found in the support archive:

If PCI is not used in your design you need to look at the following. You still need to double check with both the PCI user's guide - SPRU642 and the C6205 datasheet:

1) To save some power you could consider as putting the PCI block into power down state D3cold, and as for the other pins of the PCI interface
- PCLK, 3.3VAuxDET, PIDSEL, XSP_DI could be pulldown to the GND.
- 3.3VAux pull up to the VCC.
You could consider using ~20kOhm for the pullup and pulldown resistors.

2) For all the other pins (except the one mentioned in section 3) it will depend if they are input, output or both:
- possibly one of the most important design for test and debug considerations is to make sure you properly tie off all input signals that are not being actively driven, especially those that may cause some effect on the system if they change state randomly, as they might if they're left unconnected.
- inputs that are connected to signals that sometimes go high impedance should also be carefully considered.
- unused outputs, on the other hand, can be left unconnected.
- unused I/O pins can either be handled as inputs, or configured as outputs and left unconnected.

3) PCI selection, autoinitialization and boot:
Having the PCI operation set to disable should be enough provided that you do not use PCI/HOST boot mode.
There should not be any EEPROM accesses performed for PCI autoinit if PCI is disabled since the following conditions need to be met for PCI autoinit to take place:
 - configuration pin EEAI is enabled
 - EESZ pins indicate a valid configuration
 - PCI operation is selected

Regarding PCI/host boot:
As for the PCI boot mode mentioned in section 11, page 35, it looks like the presence of the EEPROM is detected only at the second step, if the host boot mode (PCI boot) is selected.
That means if you make sure that the DSP is not configured for host boot mode, this second step (the optional EEPROM read) should not even happen, and the EMIF pins related to these PCI configuration options could be ignored, as the host boot process should not take place and the sampled value on EEAI and EESZ should be irrelevant. So first of all make sure that you select a boot mode that is not host boot mode, by connecting the proper pull ups and pull downs on the EMIF pins that configure the bootmode.

You can double check the spru642, boot mode and configurations for the C6205 at
 http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=spru642
to make sure that you do not select a (PCI) host boot mode, depending on the memory map you would like to use.  (See the table 5 for a list of the bootmode configuration pins, and table 7 for the boot device configuration and description).

Please note that the RESERVED fields of table 7, corresponding to the respective EMIF data lines, should be pulled down.

4) Besides the PCI configuration, very important is also to follow the specification for the reserved for test pins, at page 18 of the datasheet, please find the link below for your reference
http://www-s.ti.com/sc/ds/tms320c6205.pdf

5) The C6416 HW design guide can as well be helpfull even if it is C6416 related. The section 4 give some good design and debug practises that can be used for C6205 as well:
 http://focus.ti.com/dsp/docs/dspsupporttechdocsc.tsp?sectionId=3&tabId=409&familyId=477&abstractName=spra943b

6) If PCi is not used at all then it means that neither PCLK nor PRST will be provided (ie pull up/down accordingly). According to the RESET section of the PCI specs the AD[] pins should be tri-sated as long as the PRST has not been released. So you might leave the pin floating since it should be tri-stated.

Still it might be safer to have external pull down if for some reason the PCI peripherals still goes to an active state.