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AM5728: Questions about "DDR1_a[0:15]"

Darren (FAE)
Expert 5483 points
Part Number: AM5728

The AM5728 has the address pin DDR1_a[0:15] for EMIF.
I need some clarification on the function of this pin.

An application I'm supporting is considering a way to check if there is a short/open in the signal connections between AM5728 and DDR3.
One way to do this under consideration, is to use an address where pins next-to each other are a different voltage level.

For example, if one address pin is "Low" then the address pin next to it would be "High".
This way no two pins next to each other will be both "Low" or "High"

Could you help provide comments on the address / how to use ddr1_a[0:15] for this?

Looking at the memory map in the TRM, I understand the below ranges are for the EMIF.
But it seems given the address bus has only 16pins, it feels like these can't be set...?
Q2: 0x8000_0000～0xBFFF_FFFF
Q3: 0xC000_0000～0xFFFF_FFFF

  • 0
    TI__Mastermind 30035 points

    Hi,

    DDR3 is organized into banks of memory, where each bank has rows and columns. Thus when accessing a particular memory location, the address is determined by the bank, row, and column.

    The bank is determined by the bank address (BA[2:0]) pins. The row is determined by the address (A[15:0]) pins during an ACT command. The column is determined by A[11,9:0] during a READ or WRITE command.

    The EMIF inside the AM5728 will convert the system address (ex: 0x80000000) to a specific bank, column, and row when trying to access the DDR3 memory. Exact mapping will depend on the memory being used (size / architecture), whether the EMIF data bus is configured for16-bit or 32-bit , as well as the IBANK_POS parameter.

    You can find more information in the TRM, see section 15.3.4.12 SDRAM Address Mapping

    https://www.ti.com/lit/pdf/spruhz6 

    Regards,
    Kevin