AM3352: BALL RESET STATE and BALL REST REL.

Hello Astro, 

Thank you for the query.

If the "High" status of the pin is not tolerated even for a moment by the application, the BALL RESET STATE and BALL RESET REL. STATE are both concerned with the need to select a "Low" GPIO.

I agree with your assessment on selecting the IO with low condition.

Regards,

Sreenivasa

Hi, Sreenivasa

Thank you for your advice.
Am I correct in understanding that when either BALL RESET STATE or BALL RESET REL. STATE is "High" on a pin, there is a possibility that the pin may go ”High” even for a moment while the power is interrupted?

Thanks,
Astro

Hello Astro,

Please refer to the below note 

The state of the pins can be anything during power ramp up or down.  The pin state shown in the Pin Attributes table is only valid while all power rails are valid.   The IO supply voltage must remain valid and never change voltage while the device reset is de-asserted.

Regards,

Sreenivasa

Hello Astro,

Am I correct in understanding that when either BALL RESET STATE or BALL RESET REL. STATE is "High" on a pin, there is a possibility that the pin may go ”High” even for a moment while the power is interrupted?

Assuming you did not make any changed in the application, the pin will always be high. 

During Power interruption - Power ramp or power down, as mentioned above the state of the pins are not defined.

Regards,

Sreenivasa