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AM5718: to interact with eMMC 5.1 flash need firmware change compare to 5.0

srikanth chandrasekaran
Prodigy 10 points
Part Number: AM5718
Other Parts Discussed in Thread: CSD

Our current design use the NAND flash IS21ES16G-JCLI , which is not recommended for new design and recommended replacement is IS21TF16G-JCLI. Supplier suggested this part as FFF replacement. However could see some difference in hex values of CSD and ECSD registers. My query is any firmware change is required to interact with new flash chip?. If changes required means, only the initialization register value to be changed ?. Where can i find the list of eMMC flashes  supported by AM5718 processor, 

  • 0
    TI__Intellectual 1230 points

    Hello,

    Please see the related E2E question on this regarding using eMMC 5.1 devices in place of 5.0: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/927534/am5728-mmc2-interface-compatibility-with-emmc-version-5-1

    Backwards compatibility should be supported, and any CSD/ECSD register differences should only reflect extended functionality on the 5.1 compliant device.

    Regards,

    Marco

  • 0 in reply to Marco Garcia
    Prodigy 10 points

    Thank you Marco for confirming.  Below are list of difference in registers  and corresponding hex values.  Specifically the CRC value is different, in this case how processor will interact  with new 5.1 version  eMMC chip without firmware/software modification? 

    CSD register Byte size Bytes  Hex values
    IS21ES16G-JCLI (existing part)    		 Hex values
    IS21TF16G-JCLI(recommended alternate)
    CRC     30h 2Eh
    ECSD        
    Max packed read commands 1 [501] 3Ch 20h
    Large Unit size 1 [495] 07h 18h
    Supported modes 1 [493] 1h 3h
    FFU Argument 4 [490:487] 65535 0h
    barrier support 1 [486] Not available  0h
    firmware version 8 [261:254]     
    cache size 4 [252:249]  1024 1536
    Generic CMD6 timeout 1 [248] 19h Ah
    power off notification timeout 1 [247]  FFh 32h
    1st intitalization time after partitioning 1 [241]  64 1Eh
    Minimum Write Performance for
    8bit at 52MHz in DDR mode     		 1 [235] 0h 4Bh
    TRIM Multiplier 1 [232]  55h 12h
    Secure Erase Multiplier  1 [230] 25h 64h
    Secure TRIM Multiplier 1 [229] 25 64h
    High-capacity erase timeout  1 [223]  11h 12h
    Production state awareness
    Timeout    		 1 [218]  14h 0h
    Minimum Write Performance
    for 8bit at 52MHz    		 1 [210] 8h 4Bh
    Minimum Read Performance
    for 8bit at 52MHz    		 1 [209] 8h 0h
    Minimum Write Performance
    for 8bit at 26MHz, for 4bit at
    52MHz    		 1 [208] 8h 2Bh
    Minimum Read Performance
    for 8bit at 26MHz, for 4bit at
    52MHz    		 1 [207] 8h 0h
    Minimum Write Performance
    for 4bit at 26MHz    		 1 [206] 8h 1Eh
    Minimum Read Performance
    for 4bit at 26MHz    		 1 [205] 8h 0h
    Out-of-interrupt busy timing  1 [198] 4h ah
    Write reliability parameter
    register    		 1 [166] 04h 15h
    Enable background operations
    handshake    		 1 [163] 0h 2h
    Max Enhanced Area Size  3 [159:157]  932 618
    Max pre loading data size 4 [21:18] 15204352 9932800
  • 0 in reply to srikanth chandrasekaran
    TI__Intellectual 1230 points

    Hello Srikanth,

    I have consulted with the software expert, and they confirmed that there should be no backwards compatibility issues or changes required.

    -Marco