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Flash V1.5.1.0 Problem

Other Parts Discussed in Thread: SYSCONFIG

I am having trouble programming the NAND flash using Flash v1.5.1.0.  Last week, I was able to program 3 out of 5 boards and I loaded a DRAM program through UBoot on two of them.  Both board ran over the weekend without any DRAM failure.

However, I can’t program the flash using Flash v1.5 on all my boards now.  They are all sticking at the “Waiting for 2nd” step.  Below is the message from the console.  I am pretty sure the HW is working since the DRAM test program loads and executes every time I cycle power. 

¯ -stdout

¯ -omap 3

¯ -com 1

¯ -t 60

¯ -p EVM_MDDR_MICRON_2G_EMIF

¯ -2

¯ chip_erase NAND 0

¯ Leaving parameter file:temp_script.txt

¯ @temp_script.txt

¯ Looking for device (omap com1)

¯ Please turn off device, then turn it on again

¯ Awaiting ASIC id

¯ AsicId items 04

¯ AsicId id 01 05 01 34 30 07 58

¯ AsicId secure_mode 13 02 01 00

¯ AsicId public_id 12 15 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

¯ AsicId root_key_hash 14 15 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

¯ Searching 2nd for: EVM_MDDR_MICRON_2G_EMIF 343007 58 GP

¯ Loading second file Targets\2nd-Downloaders\dnld_startup_omap3_gp_2g.2nd

¯ Entering parameter file:omapflash2nd.txt at line: 15

¯ -pheriphalboot_reopen

¯ Reading board configuration file Targets\Configurations\configuration_am35xxevm_micron_2g.txt

¯ Reading definition file .\targets\definitions\definitions_omap3.txt

¯ -board_config Targets\Configurations\configuration_am35xxevm_micron_2g.txt

¯ Leaving parameter file:omapflash2nd.txt

¯ Sending size of second file (0x00006804 bytes)

¯ Transferring second file to target (0x6804 bytes)

¯ Closing boot connection

¯ Found device (omap com1)

¯ Waiting for 2nd

¯ Reception failed - timeout after 60 s during peripheral boot (waiting for 2nd)

 

Console program failed, exit code: 2

  • Do you have the same NAND and SDRAM memory device types as the AM3517EVM?

    Regards,

    Michael T

  • The SDRAM is the exact same one as the EVM.  The flash is MT29F2G16 and the EVM has a MT29F4G16.  I also want to point out that I am using the internal 32k clock instead of a external 32k crystal.  I am not sure if the flash utility uses that.

  • Ron:

    You may need to customize the target configuration file that Flash Tool is using.  Just select

    Custom AM35xx Board, for example and modify the file.  It contains all the register settings

    that are applied to setup clocks, DPLLs, and SDRAM and GPMC interfaces.

    Regards,

    Michael T

    Regards,

    Michael T

    PS: Please mark this post as answered via the Verify Answer button below if you think it answers your question.  Thanks!

     

  • Ron,

    Can you please post the content of the following file:

    Targets\Configurations\configuration_am35xxevm_micron_2g.

    Thanks

    Tiemen

  • # Specify platform memories

    # Do not set bberase to 1 unless you know what you are doing - it will cause factory-marked bad blocks to be marked as good and cannot be undone
    memory NAND          driver Targets\Flash-Drivers\nand_onfi_16bit_8bit.bin parameters gpmc 0x6E000000 cs 0 address 0x30000000 bberase 0
    memory NANDBCH4      driver Targets\Flash-Drivers\nand_onfi_16bit_8bit.bin parameters gpmc 0x6E000000 cs 0 address 0x30000000 bberase 0 bch   4
    memory NANDBCH8      driver Targets\Flash-Drivers\nand_onfi_16bit_8bit.bin parameters gpmc 0x6E000000 cs 0 address 0x30000000 bberase 0 bch   8
    memory NANDSWECC     driver Targets\Flash-Drivers\nand_onfi_16bit_8bit.bin parameters gpmc 0x6E000000 cs 0 address 0x30000000 bberase 0 swecc 1
    memory NANDINTECC    driver Targets\Flash-Drivers\nand_onfi_16bit_8bit.bin parameters gpmc 0x6E000000 cs 0 address 0x30000000 bberase 0 intecc 1
    memory NANDINFO      driver Targets\Flash-Drivers\nand_onfi_16bit_8bit.bin parameters gpmc 0x6E000000 cs 0 address 0x30000000 bberase 0 onfi 0 bpp 2048 sbpp 64 ppb 64 bpl 4096 l 1 acv 0x23 f 0x0019
    memory NANDINFOBCH4  driver Targets\Flash-Drivers\nand_onfi_16bit_8bit.bin parameters gpmc 0x6E000000 cs 0 address 0x30000000 bberase 0 onfi 0 bpp 2048 sbpp 64 ppb 64 bpl 4096 l 1 acv 0x23 f 0x0019 bch 4
    memory NANDINFOBCH8  driver Targets\Flash-Drivers\nand_onfi_16bit_8bit.bin parameters gpmc 0x6E000000 cs 0 address 0x30000000 bberase 0 onfi 0 bpp 2048 sbpp 64 ppb 64 bpl 4096 l 1 acv 0x23 f 0x0019 bch 8
    memory NANDINFOSWECC driver Targets\Flash-Drivers\nand_onfi_16bit_8bit.bin parameters gpmc 0x6E000000 cs 0 address 0x30000000 bberase 0 onfi 0 bpp 2048 sbpp 64 ppb 64 bpl 4096 l 1 acv 0x23 f 0x0019 swecc 1
    memory NANDINFOINTECC driver Targets\Flash-Drivers\nand_onfi_16bit_8bit.bin parameters gpmc 0x6E000000 cs 0 address 0x30000000 bberase 0 onfi 0 bpp 2048 sbpp 64 ppb 64 bpl 4096 l 1 acv 0x23 f 0x0019 intecc 1
    memory SDRAM         parameters address 0x80000000

    # Get device definitions

    use .\targets\definitions\definitions_omap3.txt

    # Specify OMAP configuration

    # Pin multiplexing

    MODE_32

    # secure_unlock() in am3517evm.c of xloader

    WRITE         RT_REQ_INFO_PERMISSION_1   0xFFFFFFFF
    WRITE         RT_READ_PERMISSION_0       0xFFFFFFFF
    WRITE         RT_WRITE_PERMISSION_0   0xFFFFFFFF
    WRITE         RT_ADDR_MATCH_1          0x00000000
    WRITE         GPMC_REQ_INFO_PERMISSION_0 0x0000FFFF
    WRITE         GPMC_READ_PERMISSION_0     0x0000FFFF
    WRITE         GPMC_WRITE_PERMISSION_0    0x0000FFFF
    WRITE         OCM_REQ_INFO_PERMISSION_0  0x0000FFFF
    WRITE         OCM_READ_PERMISSION_0  0x0000FFFF
    WRITE         OCM_WRITE_PERMISSION_0     0x0000FFFF
    WRITE         OCM_ADDR_MATCH_2           0x00000000
    WRITE         SMS_RG_ATT0                0xFFFFFFFF

    MODE_16

    MODIFY        CONTROL_PADCONF_SDRC_D0            0x001F     0x0 # sdrc_d0
    MODIFY        CONTROL_PADCONF_SDRC_D0_HI         0x001F     0x0 # sdrc_d1
    MODIFY        CONTROL_PADCONF_SDRC_D2            0x001F     0x0 # sdrc_d2
    MODIFY        CONTROL_PADCONF_SDRC_D2_HI         0x001F     0x0 # sdrc_d3
    MODIFY        CONTROL_PADCONF_SDRC_D4            0x001F     0x0 # sdrc_d4
    MODIFY        CONTROL_PADCONF_SDRC_D4_HI         0x001F     0x0 # sdrc_d5
    MODIFY        CONTROL_PADCONF_SDRC_D6            0x001F     0x0 # sdrc_d6
    MODIFY        CONTROL_PADCONF_SDRC_D6_HI         0x001F     0x0 # sdrc_d7
    MODIFY        CONTROL_PADCONF_SDRC_D8            0x001F     0x0 # sdrc_d8
    MODIFY        CONTROL_PADCONF_SDRC_D8_HI         0x001F     0x0 # sdrc_d9
    MODIFY        CONTROL_PADCONF_SDRC_D10           0x001F     0x0 # sdrc_d10
    MODIFY        CONTROL_PADCONF_SDRC_D10_HI        0x001F     0x0 # sdrc_d11
    MODIFY        CONTROL_PADCONF_SDRC_D12           0x001F     0x0 # sdrc_d12
    MODIFY        CONTROL_PADCONF_SDRC_D12_HI        0x001F     0x0 # sdrc_d13
    MODIFY        CONTROL_PADCONF_SDRC_D14           0x001F     0x0 # sdrc_d14
    MODIFY        CONTROL_PADCONF_SDRC_D14_HI        0x001F     0x0 # sdrc_d15
    MODIFY        CONTROL_PADCONF_SDRC_D16           0x001F     0x0 # sdrc_d16
    MODIFY        CONTROL_PADCONF_SDRC_D16_HI        0x001F     0x0 # sdrc_d17
    MODIFY        CONTROL_PADCONF_SDRC_D18           0x001F     0x0 # sdrc_d18
    MODIFY        CONTROL_PADCONF_SDRC_D18_HI        0x001F     0x0 # sdrc_d19
    MODIFY        CONTROL_PADCONF_SDRC_D20           0x001F     0x0 # sdrc_d20
    MODIFY        CONTROL_PADCONF_SDRC_D20_HI        0x001F     0x0 # sdrc_d21
    MODIFY        CONTROL_PADCONF_SDRC_D22           0x001F     0x0 # sdrc_d22
    MODIFY        CONTROL_PADCONF_SDRC_D22_HI        0x001F     0x0 # sdrc_d23
    MODIFY        CONTROL_PADCONF_SDRC_D24           0x001F     0x0 # sdrc_d24
    MODIFY        CONTROL_PADCONF_SDRC_D24_HI        0x001F     0x0 # sdrc_d25
    MODIFY        CONTROL_PADCONF_SDRC_D26           0x001F     0x0 # sdrc_d26
    MODIFY        CONTROL_PADCONF_SDRC_D26_HI        0x001F     0x0 # sdrc_d27
    MODIFY        CONTROL_PADCONF_SDRC_D28           0x001F     0x0 # sdrc_d28
    MODIFY        CONTROL_PADCONF_SDRC_D28_HI        0x001F     0x0 # sdrc_d29
    MODIFY        CONTROL_PADCONF_SDRC_D30           0x001F     0x0 # sdrc_d30
    MODIFY        CONTROL_PADCONF_SDRC_D30_HI        0x001F     0x0 # sdrc_d31
    MODIFY         CONTROL_PADCONF_SDRC_CLK           0x001F     0x0 # sdrc_clk
    MODIFY         CONTROL_PADCONF_SDRC_CLK_HI        0x001F     0x0 # sdrc_dqs0p
    MODIFY         CONTROL_PADCONF_SDRC_DQS1          0x001F     0x0 # sdrc_dqs1p   
    MODIFY         CONTROL_PADCONF_SDRC_DQS1_HI       0x001F     0x0 # sdrc_dqs2p
    MODIFY         CONTROL_PADCONF_SDRC_DQS3          0x001F     0x0 # sdrc_dqs3p

    MODIFY         CONTROL_PADCONF_SYS_BOOT7_HI       0x001F     0x8 # sdrc_dqs0n
    MODIFY         CONTROL_PADCONF_SDRC_DQS1N         0x001F     0x8 # sdrc_dqs1n
    MODIFY         CONTROL_PADCONF_SDRC_DQS1N_HI      0x001F     0x8 # sdrc_dqs2n
    MODIFY         CONTROL_PADCONF_SDRC_DQS3N         0x001F     0x8 # sdrc_dqs3n
    MODIFY        CONTROL_PADCONF_SDRC_CKE0   0x011F     0x0 # sdrc_cke0
    MODIFY         CONTROL_PADCONF_SDRC_CKE1          0x011F     0x0 # sdrc_cke1
    MODIFY         CONTROL_PADCONF_SDRC_DQS3N_HI      0x001F     0x8 # sdrc_strben_dly0
    MODIFY         CONTROL_PADCONF_SDRC_STRBEN_DLY1   0x001F     0x8 # sdrc_strben_dly1


    MODIFY         CONTROL_PADCONF_SDRC_DQS3_HI       0x011F     0x0 # gpmc_a1
    MODIFY         CONTROL_PADCONF_GPMC_A2            0x011F     0x0 # gpmc_a2
    MODIFY         CONTROL_PADCONF_GPMC_A2_HI         0x011F     0x0 # gpmc_a3
    MODIFY         CONTROL_PADCONF_GPMC_A4            0x011F     0x0 # gpmc_a4
    MODIFY         CONTROL_PADCONF_GPMC_A4_HI         0x011F     0x0 # gpmc_a5
    MODIFY         CONTROL_PADCONF_GPMC_A6            0x011F     0x0 # gpmc_a6
    MODIFY         CONTROL_PADCONF_GPMC_A6_HI         0x011F     0x0 # gpmc_a7
    MODIFY         CONTROL_PADCONF_GPMC_A8            0x011F     0x0 # gpmc_a8
    MODIFY         CONTROL_PADCONF_GPMC_A8_HI         0x011F     0x0 # gpmc_a9
    MODIFY         CONTROL_PADCONF_GPMC_A10           0x011F     0x0 # gpmc_a10
    MODIFY         CONTROL_PADCONF_GPMC_A10_HI        0x001F     0x0 # gpmc_d0
    MODIFY         CONTROL_PADCONF_GPMC_D1            0x001F     0x0 # gpmc_d1
    MODIFY         CONTROL_PADCONF_GPMC_D1_HI         0x001F     0x0 # gpmc_d2
    MODIFY         CONTROL_PADCONF_GPMC_D3            0x001F     0x0 # gpmc_d3
    MODIFY         CONTROL_PADCONF_GPMC_D3_HI         0x001F     0x0 # gpmc_d4
    MODIFY         CONTROL_PADCONF_GPMC_D5            0x001F     0x0 # gpmc_d5
    MODIFY         CONTROL_PADCONF_GPMC_D5_HI         0x001F     0x0 # gpmc_d6
    MODIFY         CONTROL_PADCONF_GPMC_D7            0x001F     0x0 # gpmc_d7
    MODIFY         CONTROL_PADCONF_GPMC_D7_HI         0x001F     0x0 # gpmc_d8
    MODIFY         CONTROL_PADCONF_GPMC_D9            0x001F     0x0 # gpmc_d9
    MODIFY         CONTROL_PADCONF_GPMC_D9_HI         0x001F     0x0 # gpmc_d10
    MODIFY         CONTROL_PADCONF_GPMC_D11           0x001F     0x0 # gpmc_d11
    MODIFY         CONTROL_PADCONF_GPMC_D11_HI        0x001F     0x0 # gpmc_d12
    MODIFY         CONTROL_PADCONF_GPMC_D13           0x001F     0x0 # gpmc_d13
    MODIFY         CONTROL_PADCONF_GPMC_D13_HI        0x001F     0x0 # gpmc_d14
    MODIFY         CONTROL_PADCONF_GPMC_D15           0x001F     0x0 # gpmc_d15

    MODIFY         CONTROL_PADCONF_GPMC_D15_HI        0x011F     0x0018 # gpmc_ncs0
    MODIFY         CONTROL_PADCONF_GPMC_NCS1          0x011F     0x0018 # gpmc_ncs1
    MODIFY         CONTROL_PADCONF_GPMC_NCS1_HI       0x011F     0x0018 # gpmc_ncs2
    MODIFY         CONTROL_PADCONF_GPMC_NCS3          0x011F     0x0018 # gpmc_ncs3
    MODIFY         CONTROL_PADCONF_GPMC_NCS3_HI       0x011F     0x0018 # gpmc_ncs4
    MODIFY         CONTROL_PADCONF_GPMC_NCS5          0x011F     0x0018 # gpmc_ncs5
    MODIFY         CONTROL_PADCONF_GPMC_NCS5_HI       0x011F     0x0018 # gpmc_ncs6
    MODIFY         CONTROL_PADCONF_GPMC_NCS7          0x011F     0x0018 # gpmc_ncs7
    MODIFY         CONTROL_PADCONF_GPMC_NCS7_HI       0x011F     0x0000 # gpmc_clk

    MODIFY         CONTROL_PADCONF_GPMC_NADV_ALE      0x011F     0x0000 # gpmc_nadv_ale
    MODIFY         CONTROL_PADCONF_GPMC_NADV_ALE_HI   0x011F     0x0000 # gpmc_noe
    MODIFY         CONTROL_PADCONF_GPMC_NWE           0x011F     0x0000 # gpmc_nwe
    MODIFY         CONTROL_PADCONF_GPMC_NWE_HI        0x011F     0x0000 # gpmc_nbe0_cle
    MODIFY         CONTROL_PADCONF_GPMC_NBE1          0x011F     0x0004 # gpio_61
    MODIFY         CONTROL_PADCONF_GPMC_NBE1_HI       0x001F     0x0000 # gpmc_nwp

    MODIFY         CONTROL_PADCONF_GPMC_WAIT0         0x001F     0x0018 # gpmc_wait0
    MODIFY         CONTROL_PADCONF_GPMC_WAIT0_HI      0x001F     0x0018 # gpmc_wait1
    MODIFY         CONTROL_PADCONF_GPMC_WAIT2         0x001F     0x001C # gpio_64
    MODIFY         CONTROL_PADCONF_GPMC_WAIT2_HI      0x001F     0x001C # gpio_65

    WAIT_N         0x100

    MODE_32

    # PRCM Configuration - AM35XX @ 166MHz L3_ICLK

    # prcm_init() of clock.c
    WRITE         PRM_CLKSEL           SYS_CLKIN_SEL_26
    WRITE         PRM_CLKSRC_CTRL      0x00000040   #SYSCLK=26

    MODIFY        CM_CLKEN_PLL_MPU     0x7                                0x5 #DPLL1 low power bypass mode
    POLL_ZERO     CM_IDLEST_PLL_MPU    0x1

    # prcm_init() of am3517evm.c in Xloader
    MODIFY        CM_CLKEN_PLL         0x7                                0x6 #PLL_FAST_RELOCK_BYPASS
    POLL_ZERO     CM_IDLEST_CKGEN      0x1

    MODIFY        CM_CLKSEL1_EMU       0x001f0000                         0x20000

    MODIFY        CM_CLKSEL1_PLL       0x07FF7F40                         0x00A60C00 #M=166,N=12,DPLL3_FCLKOUTX2=664MHz

    MODIFY        CM_CLKSEL_CORE       0xf                                0xA
    MODIFY        CM_CLKSEL_WKUP       0x6                                0x4

    MODIFY        CM_CLKEN_PLL         0xF7                               0x77 #CORE_DPLL_FREQSEL=7 PLLOCK=7  (DPLL3)
    POLL_NZERO    CM_IDLEST_CKGEN      0x1

    MODIFY        CM_CLKEN_PLL         0x00070000                         0x00010000
    POLL_ZERO     CM_IDLEST_CKGEN      0x2

    MODIFY        CM_CLKSEL1_EMU       0x1f000000                         0x03000000

    MODIFY        CM_CLKSEL_CAM        0x1f                               0x4

    MODIFY        CM_CLKSEL_DSS        0x1f                               0x9

    MODIFY        CM_CLKSEL_DSS        0x1f00                             0x1000

    MODIFY        CM_CLKSEL3_PLL       0x1f                               0x9

    MODIFY        CM_CLKSEL2_PLL       0x000FFF7F                         0x0000D80C #M=216,N=12,DPLL4_FCLKOUTX2=864MHz

    MODIFY        CM_CLKEN_PLL         0x00F70000                         0x00770000 #PERIPH_DPLL_FREQSEL=7 PLLOCK=7  (DPLL4)
    POLL_NZERO    CM_IDLEST_CKGEN      0x2

    # for OMAP35xx, need to do iva_init_34xx right here

    MODIFY        CM_CLKSEL2_PLL_MPU   0x1F                               0x01      #M2=1

    MODIFY        CM_CLKSEL1_PLL_MPU   0x7FF7F                            0x00012C0C #M=300,N=12,MPUCLK=600

    MODIFY        CM_CLKEN_PLL_MPU     0xF7                               0x77      #MPU_DPLL_FREQSEL=7,LOCK_MODE=PLL_LOCK
    POLL_NZERO    CM_IDLEST_PLL_MPU    0x1

    MODIFY        CM_CLKSEL_PER        0xFF                               0xFF
    MODIFY        CM_CLKSEL_WKUP       0x1                                0x1

    WAIT_N        0x5000

    # per_clocks_enable() of am3517evm.c

    MODIFY        CM_CLKSEL_PER        0x1                                0x1        #GPT2 = sys clk
    MODIFY        CM_ICLKEN_PER        0x8                                0x8        #ICKen GPT2
    MODIFY        CM_FCLKEN_PER        0x8                                0x8        #FCKen GPT2
    MODIFY        CM_FCLKEN1_CORE      0x2000                             0x2000    
    MODIFY        CM_ICLKEN1_CORE      0x2000                             0x2000
    MODIFY        CM_FCLKEN1_CORE      0x4000                             0x4000
    MODIFY        CM_ICLKEN1_CORE      0x4000                             0x4000
    MODIFY        CM_FCLKEN_PER        0x800                              0x800
    MODIFY        CM_ICLKEN_PER        0x800                              0x800

    MODIFY        CM_FCLKEN1_CORE      0x01000000                         0x01000000
    MODIFY        CM_ICLKEN1_CORE      0x01000000                         0x01000000
    MODIFY        CM_FCLKEN1_CORE      0x02000000                         0x02000000
    MODIFY        CM_ICLKEN1_CORE      0x02000000                         0x02000000

    WAIT_N        0x1000

    # EMIF Configuration - Micron 2 Gb (values from U-boot code - emif4.c)

    # enable DDRPHY clk
    MODIFY          0x48002584            0x8000                          0x8000   #Enable DDRPHY clk
    MODIFY          0x48002584            0x4000                          0x0000   #EMIF4A_FCLKEN=0
    MODIFY          CONTROL_IPSS_CLK_CTRL 0xF                             0xF     
    MODIFY          CONTROL_IPSS_CLK_CTRL 0x700                           0x700
    MODIFY          CONTROL_IP_SW_RESET   0x2                             0x2      #CPGMACSS_SW_RST=1

    WRITE  EMIF_DDR_PHY_CTRL_1  0x6
    WRITE   EMIF_DDR_PHY_CTRL_1_SHDW 0x6
    WRITE  EMIF_DDR_PHY_CTRL_2  0x0
    MODIFY  EMIF_IODFT_TLGC   0x400               0x400
    POLL_ZERO   EMIF_IODFT_TLGC   0x400
    POLL_NZERO   EMIF_STATUS   0x4
    MODIFY  EMIF_IODFT_TLGC   0x1                   0x1
    WRITE  EMIF_SDRAM_TIM_1  0x06668292
    WRITE  EMIF_SDRAM_TIM_1_SHDW  0x06668292
    WRITE  EMIF_SDRAM_TIM_2  0x201C320A
    WRITE  EMIF_SDRAM_TIM_2_SHDW  0x201C320A
    WRITE  EMIF_SDRAM_TIM_3  0x257
    WRITE  EMIF_SDRAM_TIM_3_SHDW  0x257
    WRITE  EMIF_PWR_MGMT_CTRL  0x80000000
    WRITE  EMIF_PWR_MGMT_CTRL_SHDW         0x80000000
    WRITE  EMIF_SDRAM_REF_CTRL  0x50F
    WRITE  EMIF_SDRAM_REF_CTRL_SHDW 0x50F
    WRITE  EMIF_SDRAM_CONFIG  0x40801432

    # GPMC configuration

    WRITE         GPMC_SYSCONFIG       0x00000010 # No idle L3 clock free running
    WRITE         GPMC_IRQENABLE       0x00000000 # All interrupts disabled */
    WRITE         GPMC_TIMEOUT_CONTROL 0x00000000 # Time out disabled


    WRITE         GPMC_CONFIG7_0       0x00000000 # Reset all GPMC CS to inactive
    WAIT_N        0x1000

    WRITE         GPMC_CONFIG7_1       0x00000000  
    WRITE         GPMC_CONFIG7_2       0x00000000  
    WRITE         GPMC_CONFIG7_3       0x00000000  
    WRITE         GPMC_CONFIG7_4       0x00000000  
    WRITE         GPMC_CONFIG7_5       0x00000000  
    WRITE         GPMC_CONFIG7_6       0x00000000  
    WRITE         GPMC_CONFIG7_7       0x00000000  

    # NAND on CS0

    WRITE         GPMC_CONFIG7_0       0x00000000
    WAIT_N        0x1000

    WRITE         GPMC_CONFIG1_0       0x00001800
    WRITE         GPMC_CONFIG2_0       0x00080800
    WRITE         GPMC_CONFIG3_0       0x00080800
    WRITE         GPMC_CONFIG4_0       0x06000600
    WRITE         GPMC_CONFIG5_0       0x00070808
    WRITE         GPMC_CONFIG6_0       0x000003cf
    WRITE         GPMC_CONFIG7_0       0x00000870

    WAIT_N        0x2000

    MODIFY        GPMC_CONFIG          0x110 0x10 # WP is made high and WAIT0 active Low */