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TDA4VM: How to evaluate the processing capability of ISP(VPAC)?

Guangyue Zhao
Prodigy 100 points

Part Number: TDA4VM

Hello TI expert

I want to know the capability of TDA4VM ISP. How many pixels it can handle? What's the loading of ISP in different conditions? 

There is "performance 1pixel/cycle" wrote in the datasheet. Is it the same to the all of the use cases? 

For example: 

Use case 1: 16bit RAW to YUV420

Use case 2: 16bit RAW to YUV422

Use case 3: 24bit RAW to YUV420

Use case 4: 16bit RAW+12bit VS to YUV420

How is the performance(?pixel/cycle) to the ISP? 

  • 0
    TI__Guru 67840 points

    Hi,

    Your question should be about VPAC-VISS (ISP).

    TDA4VM VISS runs at 720MHz with a steady state throughput of 1 pixel / cycle.
    There is some overhead for VISS pipeline setup/teardown and VISS programming between frame/camera switching.
    We typically use 600MP/s as the nominal VISS throughput counting 20% overhead.
    But, it may vary in real systems depending on the number of cameras and system DDR bandwidth limitation.

    VISS supports up to 16bit RAW input (linear or companded).
    If your case 3 is in companded RAW input to VISS, then it can be supported.

    Case 4 is supported by VISS, but it depends on your requirement on merging 16b+12b raw input.
    We normally recommend performing the WDR merging in sensor for best performance.

  • 0 in reply to Gang Hua
    Prodigy 100 points

    Hello

    Thank you for your reply. 

    For the Case4. If VPAC-VISS process the 16b+12b raw data directly. Is it also 1 pixel / cycle? or need two cycle to process the multi data of one frame? 

  • +1 in reply to Guangyue Zhao
    TI__Guru 67840 points

    Yes, it is still 1 pixel / cycle.

    The main impact is on writing raw sensor image to DDR and reading them back to VISS

  • 0 in reply to Gang Hua
    Prodigy 100 points

    Thank you very much. It's perfect solved my question.