AM6442: AM6442 MCSPI0 CS is driven but no CLK&MOSI&MISO after cycle transfer using CCS debug

jimin li

Intellectual 270 points

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG,

Dear all,

We've met a confused phenomenon for MCSPI0 transfer data using CCS XDS debug.

MCSPI0 connect with FPGA use spi 4 wire mode.

operation procedure as below:

1.power on

2. run mcspi_loopback_am64x-evm_r5fss0-0_nortos_ti-arm-clang(remove loopback in sysconfig,and change APP_MCSPI_MSGSIZE to 1) with XDS220.

We trasnfer a 8-bit 0x00 to FPGA,and the spi transfer waveform catched is right as below:

3.debug again with XDS220 without a power off.

the spi transfer waveform catched is wrong as below:

there are a twice time CS assertion,the first time is invalid, Only the sencod time is valid.

MCSPI0_CLK deassertion should be low-level,but after setp 2 it's sustain a high-level for a while.This phenomenon is right？

Soc:AM6442

MCU PLUS SDK ver:8.2.0.31

CCS ver:11.1.0.00011

syscfg:1.11.0

Thanks,

jimin.li

over 2 years ago

0 Kallikuppa Sreenivasa over 2 years ago

TI__Guru**** 189029 points

Hell jimin.li

Thank you for the query.

Is this a custom board?

Would you be able to share the interface details between the SOC and the FPGA.

Are you looping back the signals through FPGA?

Do you have a provision bypass the FPGA interface?

Are any of the other MCSPI interfaces working.

Regards,

Sreenivasa

0 jimin li over 2 years ago

Intellectual 270 points

Hi Kallikuppa Sreenivasa,

Thanks for your reply.

Yes.

Kallikuppa Sreenivasa said:
Is this a custom board?

We've walkthrough by FPGA.

There is only one spi interface in our custom board.

Thanks.

0 Kallikuppa Sreenivasa over 2 years ago in reply to jimin li

TI__Guru**** 189029 points

Hello jimin.li

Thank you for the inputs.

We've walkthrough by FPGA.

Please elaborate above statement and also provide your inputs for the below questions.

Would you be able to share the interface details between the SOC and the FPGA.

Are you looping back the signals through FPGA?

Do you have a provision bypass the FPGA interface?

Regards,

Sreenivasa

0 jimin li over 2 years ago in reply to Kallikuppa Sreenivasa

Intellectual 270 points

Hi Kallikuppa Sreenivasa,

We walkthrough just in FPGA side.

Soc can access FPGA normally by mcspi interface,so in soc side there is no walkthrough.

In FPGA side,we add CLK-count after detect CS assertion.If cs assertion ,but no CLK detection ,then decide data is not valid.

BG,

jimin.li

0 Kallikuppa Sreenivasa over 2 years ago in reply to jimin li

TI__Guru**** 189029 points

Hello imin.li

Thank you for the note. Sorry i cannot understand your inputs.

Here are a few additional questions

Would you be able to share the interface details between the SOC and the FPGA.

Is there a way to test the hardware to confirm there is no error.

Do you see the not valid data happening every time or some time.

I am trying to isolate the problem to hardware or firmware.

Regards,

Sreenivasa

0 jimin li over 2 years ago in reply to Kallikuppa Sreenivasa

Intellectual 270 points

Hi Kallikuppa Sreenivasa,

interface details your meaning is HW SCH?

Kallikuppa Sreenivasa said:
Would you be able to share the interface details between the SOC and the FPGA.

Kallikuppa Sreenivasa said:
Do you see the not valid data happening every time or some time.

the first time is right,but the second time is wrong as my debug procedure.

jimin li said:
operation procedure as below:

BG,

jimin.li

0 Kallikuppa Sreenivasa over 2 years ago in reply to jimin li

TI__Guru**** 189029 points

Hello jimin.li

Thank you for the inputs.

Can you please confirm if some information you wanted to convey is missing.

jimin li said:

operation procedure as below:

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 2 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 189029 points

Hello jimin.li

Based on the schematics provided i do not see any pullups used. Can you pls do some testing adding the pullups.

Regards,

Sreenivasa

0 jimin li over 2 years ago in reply to Kallikuppa Sreenivasa

Intellectual 270 points

hi Kallikuppa Sreenivasa,

there is no pullups in schematics,but on FPGA side we have added a pullup.You can referance below : when CS deassert ,it is a high level.

BG,

jimin.li

0 jimin li over 2 years ago in reply to Kallikuppa Sreenivasa

Intellectual 270 points

the description of operation procedure :

0 Kallikuppa Sreenivasa over 2 years ago in reply to jimin li

TI__Guru**** 189029 points

Hello jimin.li

Thank you for the inputs.

Is the behavior same without the debugger. Are you seeing the behavior on multiple boards?

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 2 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 189029 points

Hello jimin.li

In the debug mode, have you tried configuring the CS as a GPIO and toggle?

Regards,

Sreenivasa

0 jimin li over 2 years ago in reply to Kallikuppa Sreenivasa

Intellectual 270 points

hi Kallikuppa Sreenivasa,

no,we config CS pin in sysconfig as a CS function in CCS IDE.

Kallikuppa Sreenivasa said:
In the debug mode, have you tried configuring the CS as a GPIO and toggle?

No,We only tired to access mcspi by CCS demo with debugger.

No,only one of our custom boards(AM6442) use mcspi. Besides,mcspi is a backup channel in our board.GPMC is the best choice. Now we can access FPGA by GPMC normally,so mcspi is not be used anymore.

Kallikuppa Sreenivasa said:
Is the behavior same without the debugger. Are you seeing the behavior on multiple boards?

thanks,

jimin.li

0 Kallikuppa Sreenivasa over 2 years ago in reply to jimin li

TI__Guru**** 189029 points

Hello jimin.li,

Thank you for the note and explanation.

Glad to hear you have the required interface working.

I will go ahead and clos the thread.

Regards,

Sreenivasa

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AM6442: AM6442 MCSPI0 CS is driven but no CLK&MOSI&MISO after cycle transfer using CCS debug