TMS320DM6437: Unknown Behavior on Data Line YOut[7] in YCC8 mode

Thank you Paul for your reply.

We have not used DAC. We are interested only in digital output ((currently configured in YCC8 mode).  BASEPX, BASEPY, VIDWINnXP/YP/XL/YL registers changes also not providing any update.

We have used non-standard mode.

I have attached following for your reference.

1. OSD Register Snapshot

2. VENC Register Snapshot

3. HSYNC, Data lines timing diagram

4. Output image with vertical black band 

Can you please guide me as to how to go about troubleshooting this problem?  Is there any document (apart from the VPBE user guide) that can explain how osd & VENC interact..right from picking from memory & inserting the data on the output lines (for the given timing)  ?

- Abhijeet

Abhijeet,

I see. If you are using non-standard mode, you can try tweating the following parameters.

HSPLS − Horizontal sync width
HSYNC − Horizontal sync
HINT − Horizontal interval between HD
HSTART − Horizontal start of valid data
HVALID − Horizontal valid area
VSPLS − Vertical sync width
VSYNC − Vertical sync
VINT − Vertical interval between HD
VSTART − Vertical start of valid data
VVALID − Vertical valid area

regards,

Paul

Hello Paul,

Thank you for your reply.

We have tried tweaking these parameters but unable to get rid of the problem.

As you can see the output image diagram & Hsync, Data lines diagram shows that image is appearing on the output device. 

The HSYNC, VSYNC, Data lines timing are also as per the expections.

Only the YOut[7] data line behavior is different than other data lines YOut[0-6]. We are debugging for this specific issue.

If you can suggest us the setting which might get rid of this problem related ot YOut[7] data line behavior, it will be really helpful for us.

Thanks & Regards,

Abhieet

Hello Paul,

I agree with you answer. The change in the waveform is possible only by doing the tweaking VENC parameters. We are continuing with this approach.

About your questions,

1. YES. Between the two horizontal red bars, is it exactly 15-16 clock cycles.

2. YES. Initilal data (15-16 Pixel data/Cycles) on the YOut[7] always remains constant (1010101010). VENC is outputing 0x80, 0x00, 0x80, 0x00 for initilal data (15-16 Pixel data/Cycles). We think that this is the reason of the black bar.

3. The white line is drawn by me to show the vertical black band. Actuallly it is not appearing in the image.

Few more inputs found during debugging,

Scenario 1: When we send ALL ZERO (0x00) data through VPBE on the data lines.  Observations on the DSO are

1. Initilal data (15-16 Pixel data/Cycles) on the YOut[7] always remains constant (1010101010) for all the frames.

2. YOut[7] data line shows garbage data for 1088 cycles for few of the frames (Not for all). For other frames the data appears to be zero (Except initial data).

3. YOut[0-6] shows the zero data consistently. It is as per the expectations.

Scenario 2: When we send ALL (0xFF) data through VPBE on the data lines.  Observations on the DSO are

1. Initilal data (15-16 Pixel data/Cycles) on the YOut[7] always remains constant (1010101010) for all the frames.

2. YOut[7] data line shows garbage data for 1088 cycles (HVALID period) for few of the frames (Not for all). For other frames the data appears to be 0xFF (Except initial data).

3. YOut[0-6] shows the 0xFF data consistently. It is as per the expectations

Thanks & Regards,

Abhijeet

Abhijeet,

Could you please first double check whether the black bar is exactly 8 pixels wide? Are you saying no matter how you tweak the parameters, the bar always has the same width?

regarding #2 in both scenarios, several questions:

how many horizontal lines? what's the relative location with respect to vsync? always at the same locatiion? visible on the display?

regards,

Paul

Hello Paul,

1. YES. The black bar is exactly 8 pixels (16 Cycles) wide.

2. YES. No matter how you tweak the parameters, the bar always has the same width.

Regarding both scenarios (With Some update): (Total image size: 544*360*2, Image Width: 544, Image Height 360)

1. YOut[0-6] lines shows the relative correct data accross the complete HVALID period of HSYNC data. One difference observed (visible in the waveform too),  the YOut[0-6] starts after 16 cycles of HSYNC rising edge. However with our timing requirement, it shall start with HSYNC rising edge.

2. YOut[7] line shows the same initilal 16 cycles data (1010101010)  for all horizontal lines (360 lines). The relative locations are available in the register dump given above.

In short the VENC parameters below,

HINT: 2340

VINT: 385

HVALID: 1088

VVALID: 360

HSPLS: 1252

VSPLS: 5

VSTART: 15

HSTART: 0 (Actually needs to be 1252 & HSDLY, VSDLY shall be 0. If we do so, the data on data lines YOut[0-7] becomes unavailable)

HSDLY: 0x450 (The reason is given in HSTART setting)

VSDLY: 0x450 (The reason is given in HSTART setting)

With above mentioned settings, we are able to get the output image attached in this post. If you need any more information apart from this, please let me know.

Thanks & Regards,

Abhijeet A Rahatekar

Hello Paul,

We are able to get rid of Vertical black band issue by tweaking the values of HSDLY & HVALID.

Thanks for you help to resolve this issue.

Thanks & Regards,

Abhijeet