TDA4VM: PDN-0C Questions

Hi Team,

Any update on this?

I'm not sure this scheme will work since the SoC's MCU GPIO that you show enabling the 1st stage power converter is dependent upon the 1st stage Vo = VSYS_3V3 to supply power to the PMIC & SoC.  How does the 1st power up seq execute?

Hi Bill,

Thank you. I will update you once I have more information.

Regards,

Marvin

Hi Bill,

Thank you for waiting. 

The customer would like to understand if they need another power to supply SoC's MCU GPIO in standby mode, and if can it use the least current to keep the MCU working.

They would also want to know which power is ON as the SoC's MCU is in standby mode?, and if they need to isolate the SoC and MCU power.

I hope you can help further. Let me know if you needed more information.

Regards,

Marvin

Please download the following PMIC user's guide that describes in detail the SoC PDN power mapping and overall operation. Section 3 describes PDN power resource & GPIO control signal mappings. If there are additional questions regarding your product's design, then please list your specific concerns in reference to sections, figures &/or tables in this User's Guide.   

This PDN-0C supports 2x low power modes (MCU Only & DDR Retention) along with 3x additional optional end product features. The optional features & low power modes can be easily removed to reduce PDN BOM & area if an end product does not need these features.

Here's the TI website link below or simply search on TDA4VM and find this User's Guide under the Technical Documents:

Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for J721E, PDN-0C (Rev. A)