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SK-AM62: Processors forum

Seyed M Safaei
Intellectual 540 points
Part Number: SK-AM62
Other Parts Discussed in Thread: UNIFLASH

Hi,

I'm exploring some examples in the mcu+sdk about the bootloader. I noticed that the first stage uart bootloader (which is sent by UART and will download other stages and eventually Linux using UART), is linked to run from HSM memory. Why is this the case ? from the TRM, it appears that R5 runs at boot time but HSM is the memory for the M4 processor, so why do we run from HSM memory? I would appreciate it if you explain a bit and clarify.

this is the linker I'm talking about : 

mcu_plus_sdk_am62x_08_04_00_16/examples/drivers/boot/sbl_uart_uniflash_multistage/sbl_uart_uniflash_stage1/am62x-sk/r5fss0-0_nortos/ti-arm-clang/linker.cmd

  • 0
    TI__Genius 12330 points

    hi,

    Thanks for the query. in the current Boot flow architecture due to Memory constraints of R5 we are using the HSM memory area of M4(which is Idle during boot time), going Fwd the SBL will initialize DDR in Stage1 (of a 2 stage boot flow, where Stage 1 will run out of HSM memory) and Jump to DDR for Stage 2 and HSM FW will be loaded on HSM memory.

    The M4 is a part of Security management subsystem.

    please find more details on TI Foundational Security (TIFS) and Resource Management (RM)/ Power Management (PM) services here

    You'll find useful information on TI Sitara High Security (HS) device from links below:
    1. Sitara SoC security features:
    www.ti.com/.../spry303d.pdf
    2. Sitarra SoC secure boot:
    www.ti.com.cn/.../spry305a.pdf

    Also some good reference on security in TIFS SYSFW...
    software-dl.ti.com/.../index.html

    Please let me know if this resolves your query

    Regards

    Anshu