I am using EDMA on the (DSP in the OMAP3530) to transfer data from a FPGA on nCS4 to SDRAM on nCS0. The data width of the FPGA is 16 bits.
I set ACNT to 2, and BCNT to N, where N is the number of words that I want to read from or write to the FPGA. The number of words affected in SDRAM is correct. However, I am seeing excess transactions on the Address/Data bus. This will corrupt our FPGA FIFO implementation.
The number of excess transactions depends on the value of N.
For N=1, I get 0 extra
For N=2, I get 0 extra
For N=3, I get 1 extra
For N=4, I get 0 extra
For N=5, I get 3 extra
For N=6, I get 2 extra
For N=7, I get 1 extra
This pattern of excess bytes repeats for N mod 8.
Is this related to the Note on page 1777 (SPRUF98P) regarding EDMA TR FIFO?
"NOTE: The TR pipelining depth controls the number of read TRs for a given transfer channel that
can be serviced by the source transfer controller without being serviced by the distant
transfer controller. This dictates the amount of storage required in the distant queue channel
registers for inflight TRs
The user cannot directly program burst size, as with the sDMA, but must rely on the
ACNT/BCNT and issue 1D synchronization transfers to do so."
Is there any workaround other than using 1D synch? We have no external trigger event which can generate the next next TR.
