Netra [DM816x] Configuration of DSP Codec Server EDMA3 RM

Here's a configuration for DMAN3 that should work for DSP with the configuration above for ARM such that no resource conflicts occur:-

    DMAN3.paRamBaseIndex     = 129;  // Since all Params above 128 are available for DSP, let's make it simple and start from there.

    DMAN3.numPaRamEntries    = 48;  // number of PaRAM sets exclusively usedby DMAN, application dependent

    DMAN3.numQdmaChannels    = 6;   // number of device's QDMA channels to use

    DMAN3.qdmaChannels       = [2,3,4,5,6,7]; // QDMA channels 2-7 are available for use

    DMAN3.tccAllocationMaskL = 0xFC00000F;   // bit mask indicating which TCCs 0..31 are available for use, created using above table.

    DMAN3.tccAllocationMaskH = 0xFF0F0000; // bit mask indicating which TCCs 32..63 are available for use, created using above table.

    DMAN3.numPaRamGroup[0]   = 48;  //number of PaRAM sets for scratch group 0, application dependent number.

    DMAN3.numTccGroup[0]     = 22;  //number of TCCs assigned to scratch group 0, application dependent BUT reducing this to 22 since that is the maximum number 

 //of TCCs available to DSP per table above.

The reason I am not (yet) recommending use of useExternalRM is because as of LLD _02_11_01_02 support for the platform name TI816X wasn't proper. Also LLD needs to alter it's default configuration to respect the table above.  Once those changes are made, DMAN3 can be used with useExternalRM minimizing the overall configuration that will need to be done to use it.

For now, the above configuration should be good. I have tried to add comments to indicate why it is set to a certain value. Please feel free to ask questions here, if something isn't obvious.

Gunjan said:

because as of LLD _02_11_01_02 support for the platform name TI816X wasn't proper.

I downloaded EDMA3 LLD 02_11_02_03, and I was able to get QDMA to work on the DSP, by itself with the ARM halted, on the C6A816x EVM.  I changed the RTSC .cfg file to eliminate the linker.cmd file and to permit the code to be built using xdc in EZSDK, version 5.01.01.80.  However, the issue remains of how to get QDMA on the DSP to function when Linux is running on the ARM.  I still haven't managed this.

Lee Holeva

Followed your suggestion, I am getting this error:

/ti-ezsdk_dm816x-evm_5_01_00_77/framework-components_3_21_00_17_eng/packages/ti/sdo/fc/dman3/package.xs", line 57: 

  DMAN3 Error: configured DMAN3.numPaRamEntries (base index:  129, number of entries: 48) exceeds the maximum number of PaRam entries on this Chip (128). Reduce DMAN3.numPaRamEntries and/or adjust DMAN3.paRamBaseIndex so that it is within a valid range.

gmake[1]: *** [package/cfg/bin/ti_platforms_evmTI816X/all_DSP_xe674.c] Error 1

gmake[1]: *** [package/cfg/bin/ti_platforms_evmTI816X/all_DSP_xe674.c] Deleting file `package/cfg/bin/ti_platforms_evmTI816X/all_DSP_xe674.xdl'

gmake[1]: *** [package/cfg/bin/ti_platforms_evmTI816X/all_DSP_xe674.c] Deleting file `package/cfg/bin/ti_platforms_evmTI816X/all_DSP_xe674.h'

gmake: *** [.,.executables] Error 2

make: *** [all] Error 2

So added DMAN3.maxPaRamEntries = 512

Now the dsp server  is compling.

Thanks

RV

Good catch. Too often we end up relying on DMAN3's default configuration (which was suitable only for DM6446). We should typically update all DMAN3 parameters, and not rely on any defaults.

Here is my server info file for Netra DM816x :

Do I have to set qdmaPaRamBase,ipcKeyBase to a different value or is the default okay?

RV

After configuring the DMA correctly in all_syslink.cfg per this chain and updating (and building) syslink,uboot, uimage, cmem, filesystem with EZSDK  5_01_01_80, here is what I get [all the APCY3 calls concern DMA transfers] for ARM+DSP application's  DMA operations using codec engine ti.sdo.ce.video1.VIDENC1 copy codec:

[DSP] [t=+000,078 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+E] ACPY3_activate> Enter, handle = 0x96200708

[DSP] [t=+000,084 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+2] ACPY3_activate> Copy env 64 byte from persistent 0x96200740 to scratch 0x10800000

[DSP] [t=+000,114 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+2] ACPY3_activate> Qdma channel = 2

[DSP] [t=+000,075 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+2] ACPY3_activate> QCHMAP register for this channel is 0x101c

[DSP] [t=+000,091 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+2] ACPY3_activate> QEER register for this channel is 0xfc

[DSP] [t=+000,091 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+4] ACPY3_activate> numPaRams 1, numTccs 1

[DSP] [t=+000,079 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+X] ACPY3_activate> Exit

[DSP] [t=+000,073 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+E] ACPY3_configure> Enter (handle=0x96200708, transferNo=0)

[DSP] [t=+000,111 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+2] ACPY3_configure> WaitId is the last allocated waitId

[DSP] [t=+000,106 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+4] ACPY3_configure> 1D1D transfer

[DSP] [t=+000,074 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+4] ACPY3_configure> src 0x947ff000, dst 0x947fe000, acnt 0x400, bcnt 0x1

[DSP] [t=+000,108 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+4] ACPY3_configure> bcnt reload 0x1, srcIndex 0x0, dstIndex 0x0

[DSP] [t=+000,100 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+2] ACPY3_configure> Tcc 48

[DSP] [t=+000,068 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+4] ACPY3_configure> Link this transfer to 0xffff Opt is 0x13000c

[DSP] [t=+000,098 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+E] ACPY3_start> Enter (handle=0x96200708)

[DSP] [t=+000,081 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+2] ACPY3_start> Setup IDMA for transfer from 0x10800000 to 0x9005020

[DSP] [t=+000,103 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+X] ACPY3_start> Exit

[DSP] [t=+000,067 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+E] ACPY3_wait> Enter (handle=0x96200708)

[DSP] [t=+000,081 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+X] ACPY3_wait> Exit

[DSP] [t=+000,065 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+E] ACPY3_deactivate> Enter (handle=0x96200708)

[DSP] [t=+000,098 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+2] ACPY3_deactivate> Copy 64 nBytes of env from Scratch 0x10800000 to Persistent 0x96200740

[DSP] [t=+000,138 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+2] ACPY3_deactivate> Set QCHMAP register back to NULL param 0x101c

[DSP] [t=+000,096 us] [tid=0x94a8a72c] ti.sdo.fc.acpy3: [+X] ACPY3_deactivate> Exit

Since it is a copy codec, I did a diff on in.dat and out.dat, they match correctly. Here is what my all_syslink.cfg [in /ti-ezsdk_dm816x-evm_5_01_01_80/codec-engine_3_21_00_13_eng/examples/ti/sdo/ce/examples/servers/all_codecs] DMAN3 configuration for codec server looks like:

DMAN3.qdmaPaRamBase  = 0x09004000; //set for netra evm

DMAN3.maxPaRamEntries = 512;

DMAN3.paRamBaseIndex     = 129;  // Since all Params above 128 are available for DSP, let's make it simple and start from there.

DMAN3.numPaRamEntries    = 48;  // number of PaRAM sets exclusively usedby DMAN, application dependent

DMAN3.nullPaRamIndex = 128;  //By default, PaRam 0 is used, but often QDMA channels by default are mapped to PaRam 0, so lets switch to something safer.

DMAN3.numQdmaChannels    = 6;   // number of device's QDMA channels to use

DMAN3.qdmaChannels       = [2,3,4,5,6,7]; // QDMA channels 2-7 are available for use

DMAN3.tccAllocationMaskL = 0xFC00000F;   // bit mask indicating which TCCs 0..31 are available for use, created using above table.

DMAN3.tccAllocationMaskH = 0xFF0F0000; // bit mask indicating which TCCs 32..63 are available for use, created using above table.

DMAN3.numPaRamGroup[0]   = 48;  //number of PaRAM sets for scratch group 0, application dependent number.

DMAN3.numTccGroup[0]     = 22;  //number of TCCs assigned to scratch group 0, application dependent BUT reducing this to 22 since that is the maximum number

  //of TCCs available to DSP per table above.

Gunjan, thanks much for your help.

Regards

RV

Glad to know this worked out for you.