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PROCESSOR-SDK-AM335X: TSC_ADC functional clock reference and PRCM clarification

Wendell Silva
Prodigy 20 points
Part Number: PROCESSOR-SDK-AM335X


According to AM335x TRM, the ADC clock is related to the master clock oscillator, via the PRCM module. 

However, I did not find a way to multiply / divide CLK_M_OSC via PRCM so that adc_clk would be 192MHz (for instance) for, then, be divided by ADC_CLKDIV register in order to achieve my designed sampling frequency of exactly 307200 Hz. My CLK_M_OSC is currently 25MHz and the best I got was 308641.98 Hz with Open delay = 12 and ADC_CLKDIV = 3, Avg filter = 0.

So, I'd like to confirm my understanding:

1) PRCM does not provide multiplier/divider to select a proper adc_clk from CLK_M_OSC (that is, ADC sampling rate is a directly coupled with CLK_M_OSC and the best I can do is to set ADC's open delay, ADC_CLKDIV, avg. filter, etc).

2) PRCM only allow us to turn on or turn off the adc_clk via CM_WKUP_ADC_TSC_CLKCTRL register (not the clock frequency).

3) It is not possible to achieve an ADC sampling rate of 307200 Hz with CLK_M_OSC = 25MHz.

Best regards,

Wendell.

  • 0
    TI__Guru 63535 points

    You are correct, the PRCM doesn't provide any multiply/divide function for the ADC clock. The only clock source option for ADC clock is the master oscillator.

    Please explain how you are calculating the sample rate of 308641.98 Hz when dividing a 25 MHz clock by 4 and using an OpenDelay value of 12.  I'm asking because I do not think your calculation is correct.

    Are you enabling a single step in continuous mode?  

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 20 points

    Hi Paul,

    Yes, I'm using single step differential (AIN0, AIN1) in continuous mode.

    The formula I'm using to compute the sampling rate this (I created by interpreting the TRM):

    r: adc clock div (3)

    n: average filter (0)

    b: base frequency (25000000 in this case)

    d: open delay (12)

    308641.98 Hz = f(3, 0, 12) = (25000000 / (3 * (15 * 2^0 + 12)))

    I also used to isolate d from the formula to compute the open delay sometimes, rearranging the formula's terms like this:

    fb = b = base freq = 25MHz.

    fs = s = desired sampling freq = 307200 Hz. 

    The long brackets represent the floor function (nearest lowest integer), since the open delay must always be an integer value.

    So, please, what am I missing or misinterpreting from the TRM!? Please, tell me that I'm wrong! Sweat smile

    Thanks in advance.

    Regards,

    Wendell.   

  • +1 in reply to Wendell Silva
    TI__Guru 63535 points

    It appears you missed the following comment in the CLKDIV register description. 

    Program to the value minus 1

    A CLKDIV value of 3 will divide the 25MHz clock by 4 rather than 3. However, this does not help you achieve a sample rate of 307200 Hz.

    One option is to change the AM335x reference clock from 25 MHz to 19.2 MHz, but this change will affect many other device functions. You would need to evaluate the impact of this change on all other portions of your system implementation.

    Regards,
    Paul  

  • 0 in reply to peaves
    Prodigy 20 points

    OK Paul, I forgot to mention that, in fact, I'm programming the value of ADC_CLKDIV with 2, because 3 is needed to get the closest value possible to 307200 with 25MHz. 

    I think my hardware team won't like to change the 25 MHz OSC to 19.2 MHz. However, what parameters would you use to match 307200 exactly with 19.2MHz?

    If changing OSC gets really inevitable, I found a 24.576 MHz from the same vendor. With it, I can use open delay = 5 and clock div = 4 (programming 3), yields 307200 Hz exactly.

    I'm going to mark this thread as solved, and thanks a lot for helping me on that. 

  • 0 in reply to Wendell Silva
    TI__Guru 63535 points

    For some reason I was thinking a 19.2 MHz reference clock would work, but I was wrong.

    I also lost sight of another important detail. The ADC clock frequency is limited to a range of 1 MHz to 3 MHz, with maximum sample rate of 200 kSPS. These limits are defined in the TSC_ADC Electrical Parameters table of the AM335x datasheet.

    The AM335x datasheet only defines 4 reference clock frequencies, 19.2 MHz, 24 MHz, 25 MHz, and 26 MHz, with a maximum frequency error of +/- 50 PPM.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 20 points

    Hi Paul,

    Something is not matching the specification (AM335x datasheet / TSC_ADC Electrical Parameters).

    As I was trying to explain to Megan in this thread: 

    Despite the limitation written in the datasheet, my PRU firmware tells me that:

    1. the datasheet is wrong, or
    2. the sampling rate higher than 200 kSPS I'm getting is totally by chance. 

    I have other boards showing the exact same behavior, so I tend to not believe in the option 2 and I'm really achieving sampling rates far higher than 200kSPS.

    How do you calculate the TSC_ADC sampling frequency in terms of ADC_CLKDIV, open delay, and avg filter?

    Can you check if my calculations / formulas are correct?

  • +1 in reply to Wendell Silva
    TI__Guru 63535 points

    I told you the clock divider formula was wrong. A CLKDIV value of 0 will divide by 1, a value of 1 will divide by 2, a value of 2 will divide by 3, and a value of 3 will divide by 4, etc. Everything else looks okay. The ADC may operate at a high rate, but we do not recommend it.  The ADC clock must be limited to a maximum frequency of 3.0 MHz. This is only possible when using a 24 MHz reference clock because the dividers only divide by integer values.