I see that originally the AM3358 McSPI driver had limitations preventing it from using GPIO pins as CS, but that appears to have been patched into the kernel driver some time ago. I've been trying to get my device tree setup to use several GPIO pins as chip selects, but so far to no avail. The default CS lines are working perfectly for each SPI device, but each additional one specified using various GPIOs are not. Hoping someone can spot what the problem with my configuration is.
My kernel version is 4.14.40-rt29, which while a couple years old, has the patch applied which I found to "support arbitrary GPIO's as chip selects" in spi-omap2-mcspi.c
From the device tree, the pin definitions for each of the SPI devices is done here:
localspi_pins_default: localspi_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
AM33XX_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
>;
};
mezzanine_spi_pins_default: mezzanine_spi_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x964, PIN_INPUT | MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */
AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */
AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */
AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE4) /* (D18) uart1_ctsn.spi1_cs0 */
AM33XX_IOPAD(0x9b0, PIN_INPUT | MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */
AM33XX_IOPAD(0xa34, PIN_INPUT | MUX_MODE7) /* (F15) USB1_DRVVBUS.gpio3[13] ps temp cs*/
AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE7) /* (D14) gpio0[20].spi_mes_cs2 */
>;
};
With the SPI device tree blocks here
&spi0 {
ti,spi-num-cs=<3>;
pinctrl-names = "default";
pinctrl-0 = <&localspi_pins_default>;
status = "okay";
clocks=<&dpll_per_m2_div4_ck>;
clock-names="fck";
clock-frequency=<10000000>;
cs-gpios = <0>, <&gpio0 26 0>, <&gpio2 3 0>;
/* ADC (A16) default */
spidev0:spidev@0 {
spi-max-frequency = <5000000>; /* 5MHz */
reg = <0>;
/* compatible="rohm,dh2228fv"; */
compatible="linux,spidev";
};
/* Encoder 1 CS (T11) gpio0_26 */
spidev4:spidev@1 {
spi-max-frequency = <5000000>; /* 5MHz */
reg = <1>;
/* compatible="rohm,dh2228fv"; */
compatible="linux,spidev";
};
/* Encoder 2 CS (T7) gpio2_3 */
spidev5:spidev@2 {
spi-max-frequency = <5000000>; /* 5MHz */
reg = <2>;
/* compatible="linux,spidev"; */
compatible="linux,spidev";
};
};
&spi1 {
ti,spi-num-cs=<4>;
pinctrl-names = "default";
pinctrl-0 = <&mezzanine_spi_pins_default>;
status = "okay";
clocks=<&dpll_per_m2_div4_ck>;
clock-names="fck";
clock-frequency=<10000000>;
cs-gpios = <0>, <0>, <&gpio3 13 0>, <&gpio0 20 0>;
/* Compass CS (D18) default */
spidev1:spidev@0 {
spi-max-frequency = <5000000>; /* 5MHz */
reg = <0>;
compatible="linux,spidev";
};
/* Temp Sensor (A15) default */
spidev2:spidev@1 {
spi-max-frequency = <5000000>; /* 5MHz */
reg = <1>;
compatible="linux,spidev";
spi-cs-high;
};
/* Power Supply Temp Sensor CS (F15) gpio3_13 */
spidev3:spidev@2 {
spi-max-frequency = <5000000>; /* 5MHz */
reg = <2>;
compatible="linux,spidev";
};
/* IMU CS (D14) gpio0_20 */
spidev6:spidev@3 {
spi-max-frequency = <5000000>; /* 5MHz */
reg = <3>;
compatible="linux,spidev";
};
};
What is required to not have to manually toggle these CS lines every time I read or write from my non default pin CS devices?
