TMDS64GPEVM: PC freeze connected to host PC with PCI Express End Point operation

Hello,

Thank you for your question.

I will forward your query to the PCI experts.

Regards,

S.Anil

Hello S.Anil,

Sorry for rush you. Is there any update? 

My customer is looking for answers and would appreciate it if you could tell me status.

Best regards,
O.H

Hello S.Anil,

Sorry for rush you. Is there any update? 

If you have difficulty answering the part about this topic, or if you can answer offline, please let us know which one.

Best regards,
O.H

Hello S.Anil,

Sorry for rush you. Is there any update? 

If you have difficulty answering the part about this topic, or if you can answer offline, please let us know which one.

Best regards,
O.H

Hi,

Apologies for the delay,

from the Linux driver they write to this register to change the device ID, i am checking with IP Expert for other queries.

Regards

Anshu

hi,

PCIe Support is a basic support to enable high speed Data transfer

please refer to https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_04_00_17/exports/docs/api_guide_am64x/DRIVERS_PCIE_PAGE.html

for details of PCIe supported features

O.H said:

They are using an evaluation board with a PCI Express End Point and connecting it to a host PC. However, the host PC often freezes.
Do you know what the problem is

we have not done this level of testing , but my guess would be that the Bus Enumeration is failing at times due to which PCIe is hanging

O.H said:

After the host PC recognizes the evaluation board, when they reboot the host PC, it always freezes in the state before the BIOS screen.
Does they need to add some reset process to the program?

Link initialization & Training is possibly not happening as the PCIe is not reinitializing on the endpoint side\

O.H said:

Is there a way to find out how long it takes for PCI Express initialization to complete on the AM6442 side?

Please refer to the cycle counter API for computing the time it takes to do the initialization process https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_04_00_17/exports/docs/api_guide_am64x/KERNEL_DPL_CYCLE_COUNTER_PAGE.html

O.H said:

When accessing the base address from the host PC, How can they detect read/write on R5 core?

we will need to get back on this.

Regards

Anshu

Hi Anshu,

Thank you for confirming this with IP Experts. We look forward to receiving additional information.

O.H said:

After Pcie_open() in the source code, they was able to change the vendor ID by writing the value directly to the following address
They was able to change the vendor ID.
PCIE0 Physical Address = 0D10 0044h : PCIE0_I_VENDOR_ID_REG Register

Only device ID could be changed with the following address.
PCIE0 Physical Address = 0D00 0000h : PCIE0_I_VENDOR_ID_DEVICE_ID Register

As mentioned above, the change of vendor ID and device ID seems to have been confirmed.

Best regards,
O.H

Hi Anshu,

Thank you for your support. For some reason the page was not refreshing properly and I missed the answers for the Q1, 2, 3, 5...

I have passed on the information you provided to the customer. We will contact you again if the customer has any progress or additional questions.

Best regards,
O.H

Hi,

would you want to close this thread or keep it open.

You can always open additional threads for new questions, or even Reopen a closed thread, should you have more questions on same thread.

Regards

Anshu

Hi Anshu

Sorry for the delay in replying.

Could you please tell me about the additional questions from the customer and the following unanswered questions (Q4 for VENDRO_ID/REVISIO_ID/CLASS_ID and , Q5)?

Q4:

O.H said:

Question 4
How can they change the initial value of configuration space?
After Pcie_open() in the source code, they was able to change the vendor ID by writing the value directly to the following address
They was able to change the vendor ID.
PCIE0 Physical Address = 0D10 0044h : PCIE0_I_VENDOR_ID_REG Register

Only device ID could be changed with the following address.
PCIE0 Physical Address = 0D00 0000h : PCIE0_I_VENDOR_ID_DEVICE_ID Register

Class code etc. could not be changed with the following address.
PCIE0 Physical Address = 0D00 0008h : PCIE0_I_REVISION_ID_CLASS_CODE Register

Anshu Choudhary said:

from the Linux driver they write to this register to change the device ID, i am checking with IP Expert for other queries.

Q5:

Anshu Choudhary said:

O.H said:

When accessing the base address from the host PC, How can they detect read/write on R5 core?

we will need to get back on this.

Please let me know how to change the value of configuration space and base address access to use PCI Express.

Additional Q6:

Anshu Choudhary said:

After the host PC recognizes the evaluation board, when they reboot the host PC, it always freezes in the state before the BIOS screen.
Does they need to add some reset process to the program?

Link initialization & Training is possibly not happening as the PCIe is not reinitializing on the endpoint side\

How do I re-initialize? Do I run the Pcie_LtssmCtrl function?

[customer status update].
They found out that the setting can be changed from Root Complex to End Point by switching the DIP of J34 and J35 of the TMDS64GPEVM from pins 1 and 2 to pins 2 and 3.
However, when the End Point setting is selected, the evaluation board will not boot until the host PC is powered on and the reset is released.
It was too late to load the program in CCS after turning on the host PC. Once the host PC is reset, the evaluation board is initialized and the program disappears.
Therefore, they are trying OSPI boot.

Best regards,
O.H

Hi Anshu,

We have a question about the following OSPI Boot.

O.H said:

[customer status update].
They found out that the setting can be changed from Root Complex to End Point by switching the DIP of J34 and J35 of the TMDS64GPEVM from pins 1 and 2 to pins 2 and 3.
However, when the End Point setting is selected, the evaluation board will not boot until the host PC is powered on and the reset is released.
It was too late to load the program in CCS after turning on the host PC. Once the host PC is reset, the evaluation board is initialized and the program disappears.
Therefore, they are trying OSPI boot.

Q7:They doesn't see the Bootloader log on the UART terminal when set to OSPI BOOT MODE, could you give me an idea of what might be causing this?

We thought it would work if my customer could load the program at boot time by performing the "Step 6: Flash a Hello World example" procedure in "Getting Started". However, the preceding "Flash SOC Initialization Binary" in "Step 3: EVM Setup" was not successful.

They followed the procedure and Flash became "SUCCESS", but even though they set SW2 and SW3 to OSPI BOOT MODE, the log of Bootloader was not displayed on the UART terminal.(Tried SW2 with "11001110" and "1101000")

We thought it might be related to Silicon Revision and SDK version, but it seems that "hs_fs" is not included in the file name as a log content.(The log is attached.)
H/W: TMDS64GPEVM(SR1.0)
S/W: AM64x MCU+ SDK 08.04.00(latest)

SD Boot is working well, but we don't know how to set the program created on the SD card.

Also, any updates on previous Q4, 5, 6 would be appreciated.

Best regards,
O.H

C:\ti\mcu_plus_sdk_am64x_08_04_00_17\tools\boot>python uart_uniflash.py -p COM5 --cfg=sbl_prebuilt/am64x-evm/default_sbl_null.cfg

Parsing config file ...
Parsing config file ... SUCCESS. Found 2 command(s) !!!

Executing command 1 of 2 ...
Found flash writer ... sending sbl_prebuilt/am64x-evm/sbl_uart_uniflash.release.tiimage
Sent flashwriter sbl_prebuilt/am64x-evm/sbl_uart_uniflash.release.tiimage of size 290532 bytes in 28.27s.

Executing command 2 of 2 ...
Command arguments : --file=sbl_prebuilt/am64x-evm/sbl_null.release.tiimage --operation=flash --flash-offset=0x0
Sent sbl_prebuilt/am64x-evm/sbl_null.release.tiimage of size 265908 bytes in 27.1s.
[STATUS] SUCCESS !!!
　
All commands from config file are executed !!!

Hi,

can you please post the OSPI Boot mode issue on a separate thread, please feel free to mark a reference to this thread.

Keeping questions from different sections in different threads helps us assign the right expert and that way we can help you much better.

O.H said:

SD Boot is working well, but we don't know how to set the program created on the SD card.

can you please explain this comment.

Regards

Anshu

Hi,

Anshu Choudhary said:

can you please post the OSPI Boot mode issue on a separate thread, please feel free to mark a reference to this thread.

Keeping questions from different sections in different threads helps us assign the right expert and that way we can help you much better.

I understood. I will create a new thread for Q7.

Anshu Choudhary said:

O.H said:

SD Boot is working well, but we don't know how to set the program created on the SD card.

can you please explain this comment.

Sorry for the lack of explanation. The "SOC Initialization Using SD BOOT" in "Flash SOC Initialization Binary" works fine. But we don't know how to write the application code (e.g. Hello World Example) to the SD Card and run it successfully.

Best regards,
O.H

Hi,

O.H said:

Sorry for the lack of explanation. The "SOC Initialization Using SD BOOT" in "Flash SOC Initialization Binary" works fine. But we don't know how to write the application code (e.g. Hello World Example) to the SD Card and run it successfully.

I feel the FAQ below may be useful.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1187962/faq-sk-am62-how-to-execute-code-from-external-memory

Please let me know if this helps

Regards

Anshu

Hi Anshu,

Sorry for the late reply. Thank you for your support.

Anshu Choudhary said:

O.H said:

Sorry for the lack of explanation. The "SOC Initialization Using SD BOOT" in "Flash SOC Initialization Binary" works fine. But we don't know how to write the application code (e.g. Hello World Example) to the SD Card and run it successfully.

I feel the FAQ below may be useful.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1187962/faq-sk-am62-how-to-execute-code-from-external-memory

Please let me know if this helps

We are investigating the above issue (Q7) based on the information you provided, but have not found the problem at this time.
If a problem is found, we will proceed with the investigation in a newly created thread.

Sorry, could you please tell us about the following Q4, Q5, and Q6 that have not been answered?
It would be helpful if you could tell us if they are difficult to answer.

O.H said:

Q4:

O.H said:

Question 4
How can they change the initial value of configuration space?
After Pcie_open() in the source code, they was able to change the vendor ID by writing the value directly to the following address
They was able to change the vendor ID.
PCIE0 Physical Address = 0D10 0044h : PCIE0_I_VENDOR_ID_REG Register

Only device ID could be changed with the following address.
PCIE0 Physical Address = 0D00 0000h : PCIE0_I_VENDOR_ID_DEVICE_ID Register

Class code etc. could not be changed with the following address.
PCIE0 Physical Address = 0D00 0008h : PCIE0_I_REVISION_ID_CLASS_CODE Register

Anshu Choudhary said:

from the Linux driver they write to this register to change the device ID, i am checking with IP Expert for other queries.

Q5:

Anshu Choudhary said:

O.H said:

When accessing the base address from the host PC, How can they detect read/write on R5 core?

we will need to get back on this.

Please let me know how to change the value of configuration space and base address access to use PCI Express.

Additional Q6:

Anshu Choudhary said:

After the host PC recognizes the evaluation board, when they reboot the host PC, it always freezes in the state before the BIOS screen.
Does they need to add some reset process to the program?

Link initialization & Training is possibly not happening as the PCIe is not reinitializing on the endpoint side\

How do I re-initialize? Do I run the Pcie_LtssmCtrl function?

Best regards,
O.H