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TDA4VL : RAT mapping for R5F

Prabhjot Singh
Intellectual 256 points

Other Parts Discussed in Thread: TDA4VL

Hi there,

I am working on the TDA4VL and our use case is to map the around 2GB of SOC memory to local address space of R5Fs and HSM so that they can share the information. I found this info in the TRM about the RAT in the MCU_R5FSS0 Special Features and I couldn't find much info about the accesses ID, not even in the TIFS and SDK. 

CPUn RAT base address

0x40F9_0000

CPUn RAT accesses ID

0x2 (CPU0); 0x3 (CPU1)

Can you please provide details about the above and the region control and base registers in the RAT module?

Thanks,
Prabhjot
  • 0
    TI__Mastermind 42135 points

    Hi Prabhjot,

    Can you please point me to the TRM section you are referring to? Most probably, these access ID should correspond to the RAT source ID as mentioned in the Table 8-47 of the TRM, but I'll be able to confirm after checking the TRM section you are referring.

    Regards,
    Parth

  • 0 in reply to Parth Nagpal
    Intellectual 256 points

    Hi Parth, 

    Thanks for looking into the issue. I am referring to the J721S2_TDA4VE_TDA4AL_TDA4VL_Processors_04_2022 Silicon Revision 1.0(SPRUJ08A – FEBRUARY 2022 – REVISED APRIL 2022) TRM and there is no table 8-47.

    I am referring to the Table 6-15. MCU_R5FSS0 Special Features for RAT accesses ID and control/base registers are from the TIFS code.

    Please let me know if you need any other information. I would really appreciate if you can give an example of like basic things we need to map R5Fs to SoC memory.

    Thanks and Regards,

    Prabhjot

  • 0 in reply to Prabhjot Singh
    TI__Mastermind 42135 points

    Hi Prabhjot,

    Apologies for delay in response. SDK does not have any example as such. You can refer to the GEL file though. Please check the Configure_RAT() API in J7AEP.gel GEL file. This should help you out.

    Regards,
    Parth