Decoupling analysis and the frequency of interset.

Selvaprasad M

Hi,

While performing decoupling analysis to the processor, two things are important

1. Target Impedance

2.Frequency of interest

Where, target impedance can be calculated by current and ripple voltage. But how to find the frequency of interest , like at what range of frequency to do simulation,
In most websites, they mentioned like 1MHz -100MHz. Whether it is correct?

https://www.ti.com/lit/an/swpa222a/swpa222a.pdf?ts=1667838788299&ref_url=https%253A%252F%252Fwww.google.com%252F

In this TI document, they have provided the frequency range for different power rails, how it is determined and will it vary for different processors?

over 1 year ago

0 Colin Callaghan over 1 year ago

TI__Expert 8185 points

Hi,

We provide the FOI for each device in our PDN App note. SPRAC76.

https://www.ti.com/lit/an/sprac76e/sprac76e.pdf?ts=1668616122140&ref_url=https%253A%252F%252Fwww.google.com%252F

Regards,

Colin

0 Selvaprasad M over 1 year ago in reply to Colin Callaghan

Prodigy 60 points

Hi,

Thanks for the answer, but how the frequency of interest is determined. Based on what parameter it is calculated.

0 Colin Callaghan over 1 year ago in reply to Selvaprasad M

TI__Expert 8185 points

Hi Selvaprasad,

The simulation is based on a wide number of variables that the Design Team considers, but the main components are the Package, DIE and Board models.

The SoC designer is modeling the package and DIE PDN such that it can handle frequencies outside the FOI on it’s own, but needs the board PDN to handle those inside the FOI.

It’s helpful to distill a PDN down to the basics: a board, a part, a use-case. All three need to be well defined to effectively sim and build a PDN.

Regards,

Colin

Processors

Processors forum

Decoupling analysis and the frequency of interset.