How do I make VOUT[0] adn VOUT[1] run at 148.5/1.001 MHz (i.e. 148.35 MHz not 148.5 MHz)?
In sprugx8.pdf it says:
1.11.3.1.3 Video PLL
Figure 1-72 shows the Video PLL structure. There are 4 flying adder synthesizers. The outputs of these
synthesizers are muxed with the 27 MHz reference clock to allow its selection during PLL bypass mode.
The first synthesizer provides the SYSCLK17 (VENC SD clock) to HDVPSS; this clock is always 54 MHz.
The second one provides SYSCLK13 (HD_VENC_D_CLK) for the display subsystem. HD_VENC_D_CLK
needs to support 13.5 MHz, 27 MHz, 54 MHz, 74.25 MHz, 148.5 MHz, and 161 MHz frequencies. The
third flying adder synthesizer supplies SYSCLK15 (HD_VENC_A_CLK). This clock has similar frequency
requirements as HD_VENC_D_CLK.
This devices uses on-chip DCXO using the FA-PLL. Flying adder synthesizer 1, 2, and 3 will be used for
this. Software will control the FREQ_1, FREQ_2 and FREQ_3 to track the frequency.
Thanks,
Tim.
