Hi TI：
We found that the ddr occasionally gets stuck in initialization( fun: Board_DDRChangeFreqAck ) when do power up/down pressure test, The test process that: power up -> sbl init ddr -> power down -> wait 10s -> power up repeat, The stuck position is : wait DDR_FSP_CLKCHNG_REQ（0x114080）register loop death:
Please help me how to slove this problem and What would cause this problem?
Another question：
LPDDR4 memories use frequency set points to allow the memory to easily switch between two different
frequencies without ever being in an un-trained state.But sdk8.2_qnx /home/tda4/code/sdk8_2_qnx/PSDKRA/pdk_jacinto_08_02_00_21/packages/ti/board/src/j721e_evm/include/board_ddrRegInit.h have Three frequencies：
Main purpose What is it? reqType =1 (DDRSS_PLL_FREQENCY_1 ) Is it necessary??
Hi Dakar,
Based on the screenshot, it looks like your DDR register configuration is based off of v0.6.0 of the Jacinto7 DDR Register Configuration Tool. This tool has been updated to v0.9.1 (https://www.ti.com/lit/pdf/spracu8) since then and while most updates pertain to other devices, there are a few changes that apply to TDA4VM.
Two changes in particular have helped resolve instability problems on several systems. Can you please try making the changes below to your configuration file and see if this has any impact on the failure?
Updated write DQ training pattern (from 0x7 to 0x6) to prevent invalid training results observed in some systems
- Register Updates
> DDRSS_PHY_33, PHY_WDQLVL_PATT_0
> DDRSS_PHY_289, PHY_WDQLVL_PATT_1
> DDRSS_PHY_545, PHY_WDQLVL_PATT_2
> DDRSS_PHY_801, PHY_WDQLVL_PATT_3
Improve write DQ training by increasing the minimum valid window to prevent false edge detection.
- NOTE: This change is intended to address the same issue addressed by v0.6.1 (change 1) release.
It is recommended to implement both changes.
- Register Updates (impacted parameters)
> DDRSSn_PHY_32, PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
> DDRSSn_PHY_288, PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
> DDRSSn_PHY_544, PHY_WDQLVL_CLK_JITTER_TOLERANCE_2
> DDRSSn_PHY_800, PHY_WDQLVL_CLK_JITTER_TOLERANCE_3
Left side: Old values
Right side: New values
Hi Kevin S，
Thank you for your reply，we use v0.9.1tool gen ddr params, and change DQ training 0x10200000 > 0x10400000 & 0x0c002007 > 0xC002006 ,The problem is still here with test 2000 times power down-up.
we find change DDRSS_PLL_FREQUENCY_1 from 1066500000 to 933000000,This problem did not occur with test 7000 times， Can we modify it like this,towalk around this problem?
