TDA4VM: Question about DDR Memory Map

Hi,

When modifying the memory map, then there may be some additional changes required in the PSDK QNX header files.  Please see below link and check if that helps.

9.3. How To Take Care Of Remote Core Memory Map Updates — Processor SDK QNX J721E (ti.com)

Regards,

kb

Hi Kb，

    Thanks for your reply! I have changed tiipc_mgr_private.h and SharedMemoryAllocator.c  according to the instructions. But IPC is still abnormal.

Please help analyze the reason, thanks!

    ./vision_apps_init.sh No log information of C71.

     The DEMO  apps stuck

In regards to the overall memory map changes, and the updated header files.   A common problem with changes is stale build environment pulling in older settings.  Please ensure that build steps are cleaning/scrubbing before rebuilding.

• cd vision_apps
• make sdk_clean
• make sdk_scrub
• make sdk

Regarding the C7x, take a look at the vision_apps/platform/j721e/rtos/c7x_1 content, and ensure that the values used in .c and .cmd files there reflect the memory map changes.

Will loop in a Vision Apps expert.

Regards,

kb

Hi KB,

I have rebuilt according to the way as you mentioned, but it didn't solve the problem. The .c and .cmd for c7x_1 has been changed successfully. 

So far, IPC still fails to communicate. Is there anything else that needs to be modified? uboot or the other？

Look forward to your reply

Hi,

Could you please confirm if you have made the changes in the appMmuMap() present in the file vision_apps/platform/j721e/rtos/c7x_1/main.c?
Here could you please check if the Mmu_map() is aligned with your current memory changes?

Regards,
Nikhil

Hi, Nikhil,

     Current memory is changed in file app_mem_map.h, and the macro definitions used by appMmuMap() are all from this file, Shall I need additional operations to ensure memory alignment?

/* 
 * This file is AUTO GENERATED by PyTI_PSDK_RTOS tool. 
 * It is NOT recommended to manually edit this file 
 */ 
/* 
 * 
 * Copyright (c) 2018 Texas Instruments Incorporated 
 * 
 * All rights reserved not granted herein. 
 * 
 * Limited License. 
 * 
 * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive 
 * license under copyrights and patents it now or hereafter owns or controls to make, 
 * have made, use, import, offer to sell and sell ("Utilize") this software subject to the 
 * terms herein.  With respect to the foregoing patent license, such license is granted 
 * solely to the extent that any such patent is necessary to Utilize the software alone. 
 * The patent license shall not apply to any combinations which include this software, 
 * other than combinations with devices manufactured by or for TI ("TI Devices"). 
 * No hardware patent is licensed hereunder. 
 * 
 * Redistributions must preserve existing copyright notices and reproduce this license 
 * (including the above copyright notice and the disclaimer and (if applicable) source 
 * code license limitations below) in the documentation and/or other materials provided 
 * with the distribution 
 * 
 * Redistribution and use in binary form, without modification, are permitted provided 
 * that the following conditions are met: 
 * 
 *        No reverse engineering, decompilation, or disassembly of this software is 
 * permitted with respect to any software provided in binary form. 
 * 
 *        any redistribution and use are licensed by TI for use only with TI Devices. 
 * 
 *        Nothing shall obligate TI to provide you with source code for the software 
 * licensed and provided to you in object code. 
 * 
 * If software source code is provided to you, modification and redistribution of the 
 * source code are permitted provided that the following conditions are met: 
 * 
 *        any redistribution and use of the source code, including any resulting derivative 
 * works, are licensed by TI for use only with TI Devices. 
 * 
 *        any redistribution and use of any object code compiled from the source code 
 * and any resulting derivative works, are licensed by TI for use only with TI Devices. 
 * 
 * Neither the name of Texas Instruments Incorporated nor the names of its suppliers 
 * 
 * may be used to endorse or promote products derived from this software without 
 * specific prior written permission. 
 * 
 * DISCLAIMER. 
 * 
 * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS 
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
 * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 
 * OF THE POSSIBILITY OF SUCH DAMAGE. 
 * 
 */ 
#ifndef APP_MEM_MAP_H
#define APP_MEM_MAP_H


/* L2 for C66x_1 [ size 224.00 KB ] */
#define L2RAM_C66x_1_ADDR (0x00800000u)
#define L2RAM_C66x_1_SIZE (0x00038000u)

/* L2 for C66x_2 [ size 224.00 KB ] */
#define L2RAM_C66x_2_ADDR (0x00800000u)
#define L2RAM_C66x_2_SIZE (0x00038000u)

/* Main OCRAM for MCU2_0 [ size 128.00 KB ] */
#define MAIN_OCRAM_MCU2_0_ADDR (0x03600000u)
#define MAIN_OCRAM_MCU2_0_SIZE (0x00020000u)

/* Main OCRAM for MCU2_1 [ size 128.00 KB ] */
#define MAIN_OCRAM_MCU2_1_ADDR (0x03620000u)
#define MAIN_OCRAM_MCU2_1_SIZE (0x00020000u)

/* L2 for C7x_1 [ size 480.00 KB ] */
#define L2RAM_C7x_1_ADDR (0x64800000u)
#define L2RAM_C7x_1_SIZE (0x00078000u)

/* L1 for C7x_1 [ size 16.00 KB ] */
#define L1RAM_C7x_1_ADDR (0x64E00000u)
#define L1RAM_C7x_1_SIZE (0x00004000u)

/* MSMC for C7x_1 [ size  7.78 MB ] */
#define MSMC_C7x_1_ADDR (0x70020000u)
#define MSMC_C7x_1_SIZE (0x007C8000u)

/* DDR for MCU1_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU1_0_IPC_ADDR (0x90000000u)
#define DDR_MCU1_0_IPC_SIZE (0x00100000u)

/* DDR for MCU1_0 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU1_0_DTS_ADDR (0x90100000u)
#define DDR_MCU1_0_DTS_SIZE (0x00F00000u)

/* DDR for MCU1_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU1_1_IPC_ADDR (0x91000000u)
#define DDR_MCU1_1_IPC_SIZE (0x00100000u)

/* DDR for MCU1_1 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU1_1_DTS_ADDR (0x91100000u)
#define DDR_MCU1_1_DTS_SIZE (0x00F00000u)

/* DDR for MCU2_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU2_0_IPC_ADDR (0x92000000u)
#define DDR_MCU2_0_IPC_SIZE (0x00100000u)

/* DDR for MCU2_0 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_MCU2_0_DTS_ADDR (0x92100000u)
#define DDR_MCU2_0_DTS_SIZE (0x01F00000u)

/* DDR for MCU2_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU2_1_IPC_ADDR (0x94000000u)
#define DDR_MCU2_1_IPC_SIZE (0x00100000u)

/* DDR for MCU2_1 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_MCU2_1_DTS_ADDR (0x94100000u)
#define DDR_MCU2_1_DTS_SIZE (0x01F00000u)

/* DDR for MCU3_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU3_0_IPC_ADDR (0x96000000u)
#define DDR_MCU3_0_IPC_SIZE (0x00100000u)

/* DDR for MCU3_0 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU3_0_DTS_ADDR (0x96100000u)
#define DDR_MCU3_0_DTS_SIZE (0x00F00000u)

/* DDR for MCU3_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU3_1_IPC_ADDR (0x97000000u)
#define DDR_MCU3_1_IPC_SIZE (0x00100000u)

/* DDR for MCU3_1 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU3_1_DTS_ADDR (0x97100000u)
#define DDR_MCU3_1_DTS_SIZE (0x00F00000u)

/* DDR for C66x_2 for Linux IPC [ size 1024.00 KB ] */
#define DDR_C66x_2_IPC_ADDR (0x98000000u)
#define DDR_C66x_2_IPC_SIZE (0x00100000u)

/* DDR for C66x_1 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_C66x_1_DTS_ADDR (0x98100000u)
#define DDR_C66x_1_DTS_SIZE (0x00F00000u)

/* DDR for C66x_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_C66x_1_IPC_ADDR (0x99000000u)
#define DDR_C66x_1_IPC_SIZE (0x00100000u)

/* DDR for C66x_2 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_C66x_2_DTS_ADDR (0x99100000u)
#define DDR_C66x_2_DTS_SIZE (0x00F00000u)

/* DDR for C7x_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_C7x_1_IPC_ADDR (0x9A000000u)
#define DDR_C7x_1_IPC_SIZE (0x00100000u)

/* DDR for C7x_1 for all sections, used for reserving memory in DTS file [ size 79.00 MB ] */
#define DDR_C7x_1_DTS_ADDR (0x9A100000u)
#define DDR_C7x_1_DTS_SIZE (0x04F00000u)

/* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
#define IPC_VRING_MEM_ADDR (0xA0000000u)
#define IPC_VRING_MEM_SIZE (0x02000000u)

/* Memory for remote core logging [ size 256.00 KB ] */
#define APP_LOG_MEM_ADDR (0xA2000000u)
#define APP_LOG_MEM_SIZE (0x00040000u)

/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 63.62 MB ] */
#define TIOVX_OBJ_DESC_MEM_ADDR (0xA2040000u)
#define TIOVX_OBJ_DESC_MEM_SIZE (0x03FA0000u)

/* Memory for IPC over PCIe using shared memory. MUST be non-cached or cache-coherent [ size 64.00 KB ] */
#define PCIE_QUEUE_SHARED_MEM_ADDR (0xA5FE0000u)
#define PCIE_QUEUE_SHARED_MEM_SIZE (0x00010000u)

/* Reserved Memory for RAT mapping of remote PCIe IPC shared memory. MUST be non-cached or cache-coherent [ size 64.00 KB ] */
#define PCIE_QUEUE_MIRROR_REMOTE_SHARED_MEM_ADDR (0xA5FF0000u)
#define PCIE_QUEUE_MIRROR_REMOTE_SHARED_MEM_SIZE (0x00010000u)

/* Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
#define TIOVX_LOG_RT_MEM_ADDR (0xA6000000u)
#define TIOVX_LOG_RT_MEM_SIZE (0x02000000u)

/* Memory for shared memory buffers in DDR [ size 768.00 MB ] */
#define DDR_SHARED_MEM_ADDR (0xA8000000u)
#define DDR_SHARED_MEM_SIZE (0x30000000u)

/* DDR for MCU2_0 for non-cached heap [ size 16.00 MB ] */
#define DDR_MCU2_0_NON_CACHE_ADDR (0xD8000000u)
#define DDR_MCU2_0_NON_CACHE_SIZE (0x01000000u)

/* DDR for MCU2_1 for non-cached heap [ size 112.00 MB ] */
#define DDR_MCU2_1_NON_CACHE_ADDR (0xD9000000u)
#define DDR_MCU2_1_NON_CACHE_SIZE (0x07000000u)

/* DDR for MCU1_0 for local heap [ size  8.00 MB ] */
#define DDR_MCU1_0_LOCAL_HEAP_ADDR (0xE0000000u)
#define DDR_MCU1_0_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU1_1 for local heap [ size  8.00 MB ] */
#define DDR_MCU1_1_LOCAL_HEAP_ADDR (0xE0800000u)
#define DDR_MCU1_1_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU2_0 for local heap [ size 16.00 MB ] */
#define DDR_MCU2_0_LOCAL_HEAP_ADDR (0xE1000000u)
#define DDR_MCU2_0_LOCAL_HEAP_SIZE (0x01000000u)

/* DDR for MCU2_1 for local heap [ size 16.00 MB ] */
#define DDR_MCU2_1_LOCAL_HEAP_ADDR (0xE2000000u)
#define DDR_MCU2_1_LOCAL_HEAP_SIZE (0x01000000u)

/* DDR for MCU3_0 for local heap [ size  8.00 MB ] */
#define DDR_MCU3_0_LOCAL_HEAP_ADDR (0xE3000000u)
#define DDR_MCU3_0_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU3_1 for local heap [ size  8.00 MB ] */
#define DDR_MCU3_1_LOCAL_HEAP_ADDR (0xE3800000u)
#define DDR_MCU3_1_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for c66x_1 for local heap [ size 16.00 MB ] */
#define DDR_C66X_1_LOCAL_HEAP_ADDR (0xE4000000u)
#define DDR_C66X_1_LOCAL_HEAP_SIZE (0x01000000u)

/* DDR for c66x_1 for Scratch Memory [ size 48.00 MB ] */
#define DDR_C66X_1_SCRATCH_ADDR (0xE5000000u)
#define DDR_C66X_1_SCRATCH_SIZE (0x03000000u)

/* DDR for c66x_2 for local heap [ size 16.00 MB ] */
#define DDR_C66X_2_LOCAL_HEAP_ADDR (0xE8000000u)
#define DDR_C66X_2_LOCAL_HEAP_SIZE (0x01000000u)

/* DDR for c66x_2 for Scratch Memory [ size 48.00 MB ] */
#define DDR_C66X_2_SCRATCH_ADDR (0xE9000000u)
#define DDR_C66X_2_SCRATCH_SIZE (0x03000000u)

/* DDR for c7x_1 for Scratch Memory [ size 256.00 MB ] */
#define DDR_C7X_1_SCRATCH_ADDR (0xEC000000u)
#define DDR_C7X_1_SCRATCH_SIZE (0x10000000u)

/* DDR for c7x_1 for local heap [ size 512.00 MB ] */
#define DDR_C7X_1_LOCAL_HEAP_ADDR (0x100000000u)
#define DDR_C7X_1_LOCAL_HEAP_SIZE (0x20000000u)


#endif /* APP_MEM_MAP_H */

/*
 *
 * Copyright (c) 2018 Texas Instruments Incorporated
 *
 * All rights reserved not granted herein.
 *
 * Limited License.
 *
 * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
 * license under copyrights and patents it now or hereafter owns or controls to make,
 * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
 * terms herein.  With respect to the foregoing patent license, such license is granted
 * solely to the extent that any such patent is necessary to Utilize the software alone.
 * The patent license shall not apply to any combinations which include this software,
 * other than combinations with devices manufactured by or for TI ("TI Devices").
 * No hardware patent is licensed hereunder.
 *
 * Redistributions must preserve existing copyright notices and reproduce this license
 * (including the above copyright notice and the disclaimer and (if applicable) source
 * code license limitations below) in the documentation and/or other materials provided
 * with the distribution
 *
 * Redistribution and use in binary form, without modification, are permitted provided
 * that the following conditions are met:
 *
 * *       No reverse engineering, decompilation, or disassembly of this software is
 * permitted with respect to any software provided in binary form.
 *
 * *       any redistribution and use are licensed by TI for use only with TI Devices.
 *
 * *       Nothing shall obligate TI to provide you with source code for the software
 * licensed and provided to you in object code.
 *
 * If software source code is provided to you, modification and redistribution of the
 * source code are permitted provided that the following conditions are met:
 *
 * *       any redistribution and use of the source code, including any resulting derivative
 * works, are licensed by TI for use only with TI Devices.
 *
 * *       any redistribution and use of any object code compiled from the source code
 * and any resulting derivative works, are licensed by TI for use only with TI Devices.
 *
 * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
 *
 * may be used to endorse or promote products derived from this software without
 * specific prior written permission.
 *
 * DISCLAIMER.
 *
 * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
 * OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#include <app.h>
#include <utils/console_io/include/app_log.h>
#include <utils/misc/include/app_misc.h>
#include <stdio.h>
#include <string.h>
#include <xdc/runtime/Error.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/family/c7x/Hwi.h>
#include <ti/sysbios/family/c7x/Cache.h>
#include <app_mem_map.h>
#include <app_ipc_rsctable.h>
#include <ti/csl/soc.h>
#include <ti/csl/csl_clec.h>

/* For J7ES/J721E/TDA4VM the upper 2GB DDR starts from 0x0008_8000_0000 */
/* This address is mapped to a virtual address of 0x0001_0000_0000 */
#define DDR_C7X_1_LOCAL_HEAP_VADDR (DDR_C7X_1_LOCAL_HEAP_ADDR)
#define DDR_C7X_1_LOCAL_HEAP_PADDR (0x880000000u)

static Void appMain(UArg arg0, UArg arg1)
{
    appInit();
    appRun();
    #if 1
    while(1)
    {
        printf("C71 HEART BEAT!\n");
        appLogWaitMsecs(100u);
    }
    #else
    appDeInit();
    #endif
}

void StartupEmulatorWaitFxn (void)
{
    volatile uint32_t enableDebug = 0;
    do
    {
    }while (enableDebug);
}

/* To set C71 timer interrupts */
void appTimerInterruptInit(void)
{
    CSL_ClecEventConfig   cfgClec;
    CSL_CLEC_EVTRegs     *clecBaseAddr = (CSL_CLEC_EVTRegs*)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;

    uint32_t input         = 1249; /* Used for Timer Interrupt */
    uint32_t corepackEvent = 15;

    /* Configure CLEC */
    cfgClec.secureClaimEnable = FALSE;
    cfgClec.evtSendEnable     = TRUE;
    cfgClec.rtMap             = CSL_CLEC_RTMAP_CPU_ALL;
    cfgClec.extEvtNum         = 0;
    cfgClec.c7xEvtNum         = corepackEvent;
    CSL_clecConfigEvent(clecBaseAddr, input, &cfgClec);
    CSL_clecConfigEventLevel(clecBaseAddr, input, 0); /* configure interrupt as pulse */
    Hwi_setPriority(corepackEvent, 1);
}

/* IMPORTANT NOTE: For C7x,
 * - stack size and stack ptr MUST be 8KB aligned
 * - AND min stack size MUST be 16KB
 * - AND stack assigned for task context is "size - 8KB"
 *       - 8KB chunk for the stack area is used for interrupt handling in this task context
 */
static uint8_t gTskStackMain[64*1024]
__attribute__ ((section(".bss:taskStackSection")))
__attribute__ ((aligned(8192)))
    ;

/* DRU configuration */
#define J721E_DDR_QOS_EXP_DRU_QUEUE_PRIORITY   (2)
#define J721E_DDR_QOS_EXP_DRU_QUEUE_ORDER_ID   (4)
#define J7ES_DRU_NUM_CH (5)
#define J7ES_DRU_CFG_y(i) (0x6D008000 + ((i) * 8))
#define writel(x,y) (*((uint32_t *)(y))=(x))

void setup_dru_qos(void)
{
	unsigned int channel;

	for (channel = 0; channel < J7ES_DRU_NUM_CH; ++channel) 
	{
		writel((J721E_DDR_QOS_EXP_DRU_QUEUE_ORDER_ID << 4) | J721E_DDR_QOS_EXP_DRU_QUEUE_PRIORITY, J7ES_DRU_CFG_y(channel));
	}
}

int main(void)
{
    Task_Params tskParams;
    Error_Block eb;
    Task_Handle task;

    setup_dru_qos();

    appTimerInterruptInit();

    Error_init(&eb);
    Task_Params_init(&tskParams);

    tskParams.arg0 = (UArg) NULL;
    tskParams.arg1 = (UArg) NULL;
    tskParams.priority = 8u;
    tskParams.stack = gTskStackMain;
    tskParams.stackSize = sizeof (gTskStackMain);
    task = Task_create(appMain, &tskParams, &eb);
    if(NULL == task)
    {
        BIOS_exit(0);
    }
    BIOS_start();

    return 0;
}

#include <ti/sysbios/family/c7x/Mmu.h>

uint32_t g_app_tirtos_c7x_mmu_map_error = 0;

void appMmuMap(Bool is_secure)
{
    Bool            retVal;
    Mmu_MapAttrs    attrs;

    uint32_t ns = 1;

    if(is_secure)
        ns = 0;
    else
        ns = 1;

    Mmu_initMapAttrs(&attrs);

    attrs.attrIndx = Mmu_AttrIndx_MAIR0;
    attrs.ns = ns;

    retVal = Mmu_map(0x00000000, 0x00000000, 0x20000000, &attrs, is_secure);
    if(retVal==FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(0x20000000, 0x20000000, 0x20000000, &attrs, is_secure);
    if(retVal==FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(0x40000000, 0x40000000, 0x20000000, &attrs, is_secure);
    if(retVal==FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(0x60000000, 0x60000000, 0x10000000, &attrs, is_secure);
    if(retVal==FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(0x70000000, 0x70000000, 0x10000000, &attrs, is_secure);
    if(retVal==FALSE)
    {
        goto mmu_exit;
    }

    Mmu_initMapAttrs(&attrs);

    attrs.attrIndx = Mmu_AttrIndx_MAIR4;
    attrs.ns = ns;

    retVal = Mmu_map(APP_LOG_MEM_ADDR, APP_LOG_MEM_ADDR, APP_LOG_MEM_SIZE, &attrs, is_secure);
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(TIOVX_OBJ_DESC_MEM_ADDR, TIOVX_OBJ_DESC_MEM_ADDR, TIOVX_OBJ_DESC_MEM_SIZE, &attrs, is_secure);
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(IPC_VRING_MEM_ADDR, IPC_VRING_MEM_ADDR, IPC_VRING_MEM_SIZE, &attrs, is_secure);
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(DDR_C7x_1_IPC_ADDR, DDR_C7x_1_IPC_ADDR, DDR_C7x_1_IPC_SIZE, &attrs, is_secure); /* ddr            */
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(TIOVX_LOG_RT_MEM_ADDR, TIOVX_LOG_RT_MEM_ADDR, TIOVX_LOG_RT_MEM_SIZE, &attrs, is_secure); 
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

    Mmu_initMapAttrs(&attrs);
    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
    attrs.ns = ns;
    retVal = Mmu_map(0x70000000, 0x70000000, 0x00800000, &attrs, is_secure); /* msmc  448KB      */
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

    Mmu_initMapAttrs(&attrs);
    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
    attrs.ns = ns;
    retVal = Mmu_map(0x64800000, 0x64800000, 0x00200000, &attrs, is_secure); /* L2 sram 448KB        */
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

    #if 0
    Mmu_initMapAttrs(&attrs);
    attrs.attrIndx = Mmu_AttrIndx_MAIR0;
    attrs.ns = ns;
    retVal = Mmu_map(0x64E00000, 0x64E00000, 0x00200000, &attrs, is_secure); /* L1D sram 16KB        */
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }
    #endif

    Mmu_initMapAttrs(&attrs);
    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
    attrs.ns = ns;

    retVal = Mmu_map(DDR_C7x_1_DTS_ADDR, DDR_C7x_1_DTS_ADDR, DDR_C7x_1_DTS_SIZE, &attrs, is_secure); /* ddr            */
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_VADDR, DDR_C7X_1_LOCAL_HEAP_PADDR, DDR_C7X_1_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(DDR_C7X_1_SCRATCH_ADDR, DDR_C7X_1_SCRATCH_ADDR, DDR_C7X_1_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

    retVal = Mmu_map(DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_SIZE, &attrs, is_secure); /* ddr            */
    if(retVal == FALSE)
    {
        goto mmu_exit;
    }

mmu_exit:
    if(retVal == FALSE)
    {
        g_app_tirtos_c7x_mmu_map_error++;
    }



    return;
}

void appCacheInit()
{
    ti_sysbios_family_c7x_Cache_Size  cacheSize;
    
    /* init cache size here, since this needs to be done in secure mode */
    cacheSize.l1pSize = ti_sysbios_family_c7x_Cache_L1Size_32K;
    cacheSize.l1dSize = ti_sysbios_family_c7x_Cache_L1Size_32K;
    cacheSize.l2Size  = ti_sysbios_family_c7x_Cache_L2Size_64K;
    Cache_setSize(&cacheSize);
}

void appMmuInit(void)
{
    /* This is for debug purpose - see the description of function header */
    StartupEmulatorWaitFxn();

    g_app_tirtos_c7x_mmu_map_error = 0;

    appC7xClecInitForNonSecAccess();

    appMmuMap(FALSE);
    appMmuMap(TRUE);
    
    appCacheInit();
}

/* Offset to be added to convert virutal address to physical address */
#define VIRT_PHY_ADDR_OFFSET (DDR_C7X_1_LOCAL_HEAP_PADDR - DDR_C7X_1_LOCAL_HEAP_VADDR)

uint64_t appUdmaVirtToPhyAddrConversion(const void *virtAddr,
                                      uint32_t chNum,
                                      void *appData)
{
  uint64_t phyAddr = (uint64_t)virtAddr;

  if ((uint64_t)virtAddr >= DDR_C7X_1_LOCAL_HEAP_VADDR)
  {
    phyAddr = ((uint64_t)virtAddr + VIRT_PHY_ADDR_OFFSET);
  }

  return phyAddr;
}

     Besides, I have a little doubt that if C7_1 configures failed, could it affect IPC communication of other MCU?

Hi Nikhil,

    Did you have any suggestions? Please help us to solve this issue, thanks!

Hi KB,

    Shall you please help us to solve this issue? Look forward to your reply!

Hi Zheng,

Were you able to resolve your issue, or is this still open?

regards

Suman