I'm working on a custom board and trying to get the DDR configuration correct for U-Boot. I'm using the DDR configuration tool spreadsheet, and used the spreadsheet to generate a GEL file for CCS. When I use this GEL file to configure DDR, it appears to work. I can peek and poke a few memory addresses successfully. I've ensured that the MMU and caches are off.
Taking the DTS output from the same configuration tool spreadsheet does not produce reliable results in U-Boot. I'm wondering if the configuration is close, but marginal. I'm looking for a simple DDR test pattern code I can run on one of the Cortex-R5 cores from on-chip RAM in CCS. I'm hoping that it might produce some failures that may help determine if the DDR is marginal, and also help point to why.
Do we have any simple memory test pattern code I can adapt to this test?
Thanks,
Stuart
