Greetings DSP-BIOS Champs!
Can you please help answer the following questions:
1. How does the scheduler handle the ST1 register during TSK switches, SWI posts...etc.,
2. Does the scheduler manipulate *only* the INTM and DBGM bits in the ST1 register or others as well?
a. If other bits are manipulated as well, can you please explain what is done?
3. Is it possible for you to provide us the source for HWI_enable and HWI_disable?
a. We would like to get a better understanding of the support for handling critical sections (as seen in SPRAA25)
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FYI, Here is a brief summary of the development environment I am working with:
CCS Version: CCSV4 ( Version: 4.2.1.00004 )
Target: TMS320F28335 (eZDSP from Spectrum Digital)
Emulators: XDS510 USB and XDS100v2
Software Package: spra958i.zip (from TI)
Application: \spra958i\spra958i\CCSv4\F28335_examples_CCSv4_2010Aug10\F28335_example_BIOS_flash
DSP-BIOS Version: bios_5_41_07_24
Step to Reproduce: N/A
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Thanks,
Krishna Allam
