TDA4 - MMU + TLB +Cache

bangfei zong

Prodigy 170 points

Hi, expert

We want to learn the process of memory management on the tda4 platform， include TLB、Cache、MMU、Memory...

① Can you tell me the location of the reference code? （TLB Cache MMU...）

② Do you have any reference documents about this?

Thanks

over 3 years ago

0 Keerthy J over 3 years ago

TI__Guru**** 167700 points

Hi,

The MMU configuration for A72 is done from U-Boot:

On latest SDK: ti-processor-sdk-linux-j7-evm-08_04_00_11/board-support/u-boot-2021.01+gitAUTOINC+a169f42610-ga169f42610
File: arch/arm/mach-k3/arm64-mmu.c

Caches are also enabled in U-Boot.

arch/arm/mach-k3/j721e_init.c

spl_enable_dcache

Regards,
Keerthy

0 bangfei zong over 3 years ago in reply to Keerthy J

Prodigy 170 points

Hi, expert

How does TDA4 implement 4G memory mapping through pgd/pud/pmd and pte?

Thanks

0 Keerthy J over 3 years ago in reply to bangfei zong

TI__Guru**** 167700 points

Hi,

Please try to enable CONFIG_ARM_PTDUMP, CONFIG_GENERIC_PTDUMP.

This should give a nice debugfs entry at runtime under /sys/kernel/debug/kernel_page_tables

Also by default the page size is of 4K.

Best Regards, Keerthy

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TDA4 - MMU + TLB +Cache