处理器-SDK-AM62X：AM6254 cache partition problem

坚斌李

Part Number: PROCESSOR-SDK-AM62X
Other Parts Discussed in Thread: AM6412

SDK：08.03.00.19

we have a user who has a problem with cache.

The L3 cache needs to be divided, such as 256k for two cores and 256k for the other two cores.

Because of the concern that if there is no partition, the non-real-time load is too large, will affect the real-time linux.

Therefore, I would like to ask whether there is a cache partition method

over 3 years ago

0 Pekka Varis over 3 years ago

TI__Mastermind 27050 points

Hi,

AM62x family has a 512kB L2 cache, there is no L3 cache. L1 instruction and data caches are per core. The ARM Cortex A53 does not allow cache locking or partitioning, the L2 will be shared across all cores in the cluster in all Cortex A53 devices.

AM64x family, such as https://www.ti.com/product/AM6412 , has Cortex R cores with dedicated 2MB SRAM and 128kB TCM memory that is intended for hard realtime use cases where a shared L2 cache cannot be tolerated.

Pekka

0 坚斌李 over 3 years ago in reply to Pekka Varis

Prodigy 110 points

Thank you so much for your reply

The L1 cache cannot be partitioned

L2 cache can now be partitioned, see AM64x family, such as https://www.ti.com/product/AM6412？

Whether there is a cache partition method on 6254？

Or L2 ceche does not support partitioning？

Do you mean to recommend us to use AM64

+1 Pekka Varis over 3 years ago in reply to 坚斌李

TI__Mastermind 27050 points

Sitara (applies to all other) Cortex A53 features are below. ARMv8 architecture has many optional features like cache line locking but A53 does not implement those.

坚斌李 said:
The L1 cache cannot be partitioned

A53 L1 cache is always per core.

坚斌李 said:
L2 cache can now be partitioned, see AM64x family, such as https://www.ti.com/product/AM6412？

No, L2 cache is always shared. 512kB in AM62x and 256kB in AM64x. On chip SRAM (2MB in AM64x, 64kB in AM62x) is L3 scrachpad memory (not cache) from the A53 perspective. SRAM/scratchpad usage and partitioning is up to the user of the device.

坚斌李 said:
Whether there is a cache partition method on 6254？

No. L2 cache is always shared in all Cortex A53 devices.

坚斌李 said:
Do you mean to recommend us to use AM64

The Cortex R5 on AM64x is intended for hard partitioning of realtime tasks without any sharing with A53. If your application needs to run some service with microsecond level worst case guarantees I'm suggesting you consider using AM6412 and placing the realtime task on an R5. Linux with PREEMPT RT on A53's can meet realtime worst case of maybe 50microseconds or 100microseconds.

Pekka

0 坚斌李 over 3 years ago in reply to Pekka Varis

Prodigy 110 points

What is the L2 cache sharing rule in the code？

Could you please help to ask if there is a method to modify in the uboot phase?

0 Pekka Varis over 3 years ago in reply to 坚斌李

TI__Mastermind 27050 points

On Cortex A53 there is no configuration options or rules to set. The cache is either on or off, and if on it is shared between all the cores.

Pekka

0 坚斌李 over 3 years ago in reply to Pekka Varis

Prodigy 110 points

Thank you very much for your support

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处理器-SDK-AM62X：AM6254 cache partition problem