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C6418 EMIFA with Flash-ROM, SD-RAM and some more

Chris Fiege
Prodigy 30 points

We are currently working on a DSP-board with the C6418 DSP.

Our aim is to get SD-RAM, Flash-ROM and some more stuff into the memory map.
Since our CPU runs at 600MHz we want our SD-RAM to run at 150MHz ( fCPU / 4 ). SD-RAM is mapped into CE0-space.
Additionaly we want to map Flash-ROM into CE1-space and some additional IO-Ports in CE3.

Now, we ware concerned about track-length on the PCB. Maximum track-length from the DSP to SD-RAM is about 6cm. But additinally we will get about 10cm to the most distant pin on the Flash or IO-Ports.
In our opinion 16cm track length to the Flash will be no problem becauce it is slow enough. But a total track length of 16cm for the SD-RAM at 150MHz seems to be critial. For the 3rd or 5th harmonic of 150MHz we expect impedance transformation, reflections and so o

In place of directly connecting Flash and IO-Ports to the (SD-RAM - ) Memory -Bus we are currently planning to "decouple" the SD-RAM bus from the Flash- and Periphiral-Bus using Bus Trancivers. We expect this to be best for signals on the SD-RAM bus but we are not shure if this some extra delay is acceptable for memory-timing!

 

What is your opinion about using SD-Ram, Flash and some more stuff on the same Memory-Interface? How would you / have you solved this problem?

Thanks for your time!

  • 0
    TI__Guru* 84110 points

    You can physically connect all of these devices to the EMIF bus on the C6418. And you can logically control each of them using the different CE-spaces as you have indicated.

    Your best skill at high-speed printed circuit design will be required to get the best possible speed of operation. IBIS models and board-level simulations will be required to make sure the trace length matching and impedance matching and any required termination resistors are implemented correctly. A production-quality design will be very difficult without this.

    Bus transceivers will help you reach the best possible speed on the EMIF. This will eliminate the impact of extra loading on the SDRAM bus when you add more devices on the far side of the bus transceivers.

    Achieving 133 MHz operation of the EMIF and especially SDRAM will require an external clock source to AECLKIN and will not be easy to achieve with the extra loading.

    Achieving 150 MHz operation will not be possible since the datasheet SPRS241 states on page 18 Table 2-1 that the EMIF can operate only up to 133 MHz when using SDRAM.

  • 0 in reply to RandyP
    Prodigy 30 points

    RandyP said:

    Your best skill at high-speed printed circuit design will be required to get the best possible speed of operation. IBIS models and board-level simulations will be required to make sure the trace length matching and impedance matching and any required termination resistors are implemented correctly. A production-quality design will be very difficult without this.

    Thank you! We are planning to do this to optimize our design.


    Bus transceivers will help you reach the best possible speed on the EMIF. This will eliminate the impact of extra loading on the SDRAM bus when you add more devices on the far side of the bus transceivers.


    With bus tranceivers our asynchronus timing is getting a litte worse. A read-access to the Flash-Rom is delayed approx. 10ns. This is no problem after setting up the EMIF CE-Space Control Registers. But I did not find any information about asynchronus memory-timing at boot! Where can I find this?

    Thanks so far ;)

  • 0 in reply to Chris Fiege
    TI__Mastermind 18130 points

    Chris Fiege said:
    With bus tranceivers our asynchronus timing is getting a litte worse. A read-access to the Flash-Rom is delayed approx. 10ns. This is no problem after setting up the EMIF CE-Space Control Registers. But I did not find any information about asynchronus memory-timing at boot! Where can I find this?

    Hopefully I understand your question correctly, but if you are looking for the default register values for the CECTLn registers you can find this in the EMIF User Guide. By default this peripheral is running 8-bit with the slowest possible timings for safety reasons. Take a look at p137 of the doc I linked above. Underneath each field of the register you will see something like R/W - 1111. Per the legend, this means that that field of the register is read/write and defaults to 1111 when the device powers up.