dsk6416 memory interface

Oh ok and then it's enough to preinitialize the ce2 in the dsp bios?

Yes, that should be enough to get you going assuming the peripheral registers are configured appropriately.

ok thank you for the quick answer i'll try to read the emifa with pin 75 wired and the emifa config from the bios

sorry but it doesn't work, i've made a new project with a new emifacfg (nothing changed) and preinitialized it but it always shows me values that aren't true if i want to read it (x = = *((volatile int*)(0xA0000000));)

You should be able to see values on the header, or read values from the header once the enable pin is asserted on the header as Tim suggested, perhaps there is something wrong with how the EMIF is being configured (could you post how you are configuring the EMIF?)? One suggestion for debugging this is that it is easier to just read/write values to the EMIF by using the view memory capability of CCS, this way you can debug without having to run any code.

If i try to read the memory at 0xA0000000 it always shows me 0x7FFFFFC7 after i initialized it with the gel file:

init_emif()
{
    #define EMIFA_GCTL       0x01800000
    #define EMIFA_CE1        0x01800004
    #define EMIFA_CE0        0x01800008
    #define EMIFA_CE2        0x01800010
    #define EMIFA_CE3        0x01800014
    #define EMIFA_SDRAMCTL   0x01800018
    #define EMIFA_SDRAMTIM   0x0180001c
    #define EMIFA_SDRAMEXT   0x01800020
    #define EMIFA_CE1SECCTL  0x01800044
    #define EMIFA_CE0SECCTL  0x01800048
    #define EMIFA_CE2SECCTL  0x01800050
    #define EMIFA_CE3SECCTL  0x01800054

    #define EMIFB_GCTL       0x01A80000
    #define EMIFB_CE1        0x01A80004
    #define EMIFB_CE0        0x01A80008
    #define EMIFB_CE2        0x01A80010
    #define EMIFB_CE3        0x01A80014
    #define EMIFB_SDRAMCTL   0x01A80018
    #define EMIFB_SDRAMTIM   0x01A8001c
    #define EMIFB_SDRAMEXT   0x01A80020
    #define EMIFB_CE1SECCTL  0x01A80044
    #define EMIFB_CE0SECCTL  0x01A80048
    #define EMIFB_CE2SECCTL  0x01A80050
    #define EMIFB_CE3SECCTL  0x01A80054

    /*------------------------------------------------------------------------*/
    /* This section sets the EMIF up.  Different settings are required for    */
    /* version 1 of the DSK (100 MHz EMIF) and versions 2 or 3 (120 MHz EMIF).*/
    /* The code sets EMIFB up first so it can read the board version from     */
    /* the CPLD, then completes the EMIF setup based on what it reads from    */
    /* it.  The 120 MHz configuration is used for the initial EMIFB setup     */
    /* because if the EMIF is really running at 100 MHz the timings will      */
    /* just get slower and the EMIFB accesses will still work.                */
    /*------------------------------------------------------------------------*/

    /* Setup EMIFB Version 2 (120 MHz EMIF) */
    *(int*)EMIFB_GCTL       = 0x00002060;
    *(int*)EMIFB_CE0        = 0x02a08a00;       // CE0 CPLD 8-bit
    *(int*)EMIFB_CE1        = 0x02a08a00;       // CE1 Flash 8-bit

    if (     ( Get_Board_Rev == 5 )
        || ( ( Get_Board_Rev == 4 )
          && ( Get_PLL_Select == 1 ) ) )
    {
        /* EMIFA Version 2 (120MHz EMIF) */
        *(int*)EMIFA_GCTL       = 0x00012070;
        *(int*)EMIFA_CE0        = 0xffffffd3;   // CE0 SDRAM
        *(int*)EMIFA_CE2        = 0x23228c22;   // CE2 Daughtercard 32-bit async
        *(int*)EMIFA_CE3        = 0x23228c22;   // CE3 Daughtercard 32-bit async
        *(int*)EMIFA_SDRAMCTL   = 0x47115000;   // SDRAM control
        *(int*)EMIFA_SDRAMTIM   = 0x00000750;   // SDRAM timing refresh
        *(int*)EMIFA_SDRAMEXT   = 0x001faf4d;   // SDRAM extended control
    }
    else
    {
        /* EMIFB Version 1 (100 MHz EMIF) */
        *(int*)EMIFB_GCTL       = 0x00002060;
        *(int*)EMIFB_CE0        = 0x02208800;   // CE0 CPLD 8-bit
        *(int*)EMIFB_CE1        = 0x02208800;   // CE1 Flash 8-bit

        /* EMIFA Version 1 (100 MHz EMIF) */
        *(int*)EMIFA_GCTL       = 0x00012070;
        *(int*)EMIFA_CE0        = 0xffffffd3;   // CE0 SDRAM
        *(int*)EMIFA_CE2        = 0x22a28a22;   // CE2 Daughtercard 32-bit async
        *(int*)EMIFA_CE3        = 0x22a28a22;   // CE3 Daughtercard 32-bit async
        *(int*)EMIFA_SDRAMCTL   = 0x47115000;   // SDRAM control
        *(int*)EMIFA_SDRAMTIM   = 0x00000618;   // SDRAM timing refresh
        *(int*)EMIFA_SDRAMEXT   = 0x000a8529;   // SDRAM extended control
    }
}

Could it be a problem that not all data pins and none of the adress pins are wired?

What do you have wired to the EMIF connector on the DSK, is this supposed to be a memory or do you just have the pins pulled different directions?

nightmarevs said:

Could it be a problem that not all data pins and none of the adress pins are wired?

Without address pins you would read the same value throughout the 0xA0000000 space so that part would be expected, what value you read for each word would depend on the state of the pins on the EMIF connector of the DSK, so as a test you could try pulling some of the EMIF data pins low or high and than refresh the view memory window to see if you can change the data, you may need to disable caching on the 0xA0000000 space to see this properly (clear MAR160 at 0x01848280).

I've wired a Atmega 128 to the DSK. This provides an output Voltage arount 3.5-4V

The value i get is always the same even if pin 75 isn't wired to 79

I've tried to wire the async read enable and the byte0 enable pins to ground but it doesn't help. Do i have to wire the Ground an +5 pins on the dsk with the gorund and 5v pins on the ATMEGA?

Please, has nobody an idea how i can fix the problem?
It's urgent i have less than a week left to solve the problem and finish the project.

Is anything ok with the code from the GEL i posted and the way i want to read it?

Which pins have to be wired to ground additional to the data pins and does the Atmega ground and 5V connectors need to be connected to the DSK?

Greetings

nightmarevs

It is unclear what device you have connected to the EMIF daughter card connector and how you have it connected to the signals of the C6416.

If you could provide that information it would help the discussion.

I have connected 3 Ports of an ATMEGA 128 to the 6416 and i've just wired the data pins and pin 75 to Gorund

I am not very familiar with the ATMEGA 128, but I assume you have it programmed to output some specific value to the data pins on the C6416 DSK header? I am not sure how you would synchronize between the ATMEGA 128 and the DSK without any address lines or r/w enables, what is the ATMEGA supposed to be outputting to the DSK (or vice versa)?

To debug this I would probably start at the lowest level and remove the ATMEGA from the system to see if this is a problem with what the ATMEGA is outputting or that the DSK is simply not receiving. If you simply pull the individual data pins on the DSK high or low can you see the effect reflected in the view memory window of CCS? If you probe the ATMEGA pins are they driving the way you expect them to?

The ATMEGA sends 3 7bit values and a 4 bit value paralell to the dsk so i wired only the first 25 data pins. The ATMEGA is working correct i've checked the output with a voltmeter. But if i want to read the 0xA0000000 adress on the dsk it always shows me 0x7FFFFFC7 independent of the input

I can see three reasons why this could happen, though they should already be taken care of.

1. This would fail if DC_DET was not pulled low, DC_DET goes through the CPLD and ultimately should enable the OE signals on the daughtercard buffers (U5, U6, U16, U17). It may be worth checking to ensure that the OE signal on U5 and U6 is being asserted when you attempt the read.

2. This would also fail if the direction input on the daughtercard buffers was not driving the proper direction, this should also be handled by the CPLD, though it may be worth checking to ensure the DIR signal on U5 and U6 is being asserted when you attempt the read.

3. This could fail if something else was inadvertently still driving the bus, namely the SDRAM, though this should not happen (and if it did you could have bus contention and burn out a driver), it may be worth trying this out without configuring the SDRAM just to see what happens (i.e. see if you get any different results with no GEL file).

1. This is a problem when i read the DC_REG i get the value 48

110000 according to the manual this means that the bits 6 and 7 are 0 and 7 is the Daughter Card Detect. But how can i fix that? Pin 75 is wired with pin  79?

Just to be clear, the pin that must be pulled low is pin 75 of the peripheral expansion connector J3, not the memory expansion connector J4. If you take a voltmeter to pin 75 is it really being pulled to ground?

ok i've got the failure, there was something wrong with pin 75 so there wasn't contact. Now it's working good thank you

I am glad to hear it :). I imagine you are just reading some status information from the ATMEGA? It still seems odd to just have the data bus hooked up to me, usually you would need some way of synchronizing data on the bus.

usually yes but this time it seemed to be easier that way because i have only 1 25bit variable to submit. The ATMEGA is controlling 5 I/O devices and a Display.And it's faster that way because the ATMEGA runs only at 16MHZ so it would cost time to wait for the AMTEGA to response if the dsp requests a value with the adress bus