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Hi Team,
I want to use the following pins to generate a 500K
clock.
https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/clocks.html
I checked clk and ran it, but there was no waveform output.
The dts is as follows:
elmos@0 { pinctrl-names = "default"; pinctrl-0 = <&spi_e521_clkref_pins_default>; spi-max-frequency = <2000000>; reg = <0>; compatible = "elmos,e521.42"; clocks = <&k3_clks 157 82>; clock-names = "elmos"; }; code: ref_clk = devm_clk_get(&spi->dev,"elmos"); ret = clk_prepare_enable(ref_clk); dev_dbg(&spi->dev, "elmosclk_prepare_enable ret%d\n",ret);
The results of the pinmux detection were as follows (mode 2):
But there was no waveform output to the corresponding pin.
cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty
clock count count count rate accuracy phase cycle
---------------------------------------------------------------------------------------------
clk:157:82 1 1 0 0 0 0 50000
Hello,
Is this a PWM pin?
ecap0_in_apwm_ou
Can I set it as a PWM one? If so, how can I set the output as 500k?
Kind regards,
Katherine
Is this a PWM pin?
ecap0_in_apwm_ou
Yes, it can be exported from this module, but it seems the registers of the operation module may crash.
They will also crash under the read-only mode. We are using SDK 7.3 for the time being. We tried in Linux and U-boot, and the same thing happened.
Can I set it as a PWM one? If so, how can I set the output as 500k?
Yes, as above, to generate a PWM output, a 500K square wave would be enough.
Hi Team,
The code written by us plus:
+ power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
pm_runtime_enable(&pdev->dev);
ret = pm_runtime_get(&pdev->dev);
if (ret < 0) {
pm_runtime_put_noidle(&pdev->dev);
return ret;
}
The registers of the operation module didn’t crash again for the time being.
We operated on the registers and followed the trm example but did not generate the corresponding waveform.
reg_writel(pcap,ECAP_ECCTL,reg_readl(pcap,ECAP_ECCTL) | EC_APWM_MODE<<25);
reg_writel(pcap,ECAP_CAP1,1200);
reg_writel(pcap,ECAP_CNTPHS,0x0);
reg_writel(pcap,ECAP_ECCTL,0x0);
reg_writel(pcap,ECAP_ECCTL,reg_readl(pcap,ECAP_ECCTL)&(~(1<<26)));
reg_writel(pcap,ECAP_ECCTL,reg_readl(pcap,ECAP_ECCTL)&(~(1<<21)));
reg_writel(pcap,ECAP_ECCTL,reg_readl(pcap,ECAP_ECCTL)&(~(EC_SYNCO_DIS<<22)));
reg_writel(pcap,ECAP_ECCTL,reg_readl(pcap,ECAP_ECCTL) | 1<<20);
reg_writel(pcap,ECAP_CAP2,0x300);
Could you please tell me how to operate on the ecap0 register so that the “ecap0_in_apwm_out” can have a 500K output?
Kind regards,
Katherine
Katherine,
Apologies for the long delay. Could you use ehrpwm instance on the SoC to generate waveform?
If not could you clearly explain the requirement and code changes you have done thus far?
Best Regards,
Keerthy