SDRAM burst terminate via EMIFB

Ashlesha Raut said:

My application requires me to access only one data during each read and write transaction to the SDRAM memory connected to OMAP L-137 HT processor via EMIFB bus.

Can you describe this requirement in greater detail?  What is driving that requirement? 

The SDRAM controller operates pretty much autonomously, i.e. the CPU is not involved in the nitty gritty aspects of page management, refreshes, commands, etc.  That said, I don't know of any way to force a BT command, but I still don't understand why you would even want to do that.  If you explain at a higher level what you are trying to achieve then perhaps I can suggest a better alternative that will still accomplish your goals.

Hi Brad,

The requirement is to connect SRAM and Flash memories to EMIFB bus via a FPGA. There is already some amount of SRAM and Flash memories connected to the EMIFA bus. We need more of these memories to be connected to EMIFB bus, so that the boot data can be stored in the non-volatile memory and some more applications.

The problem is, for Flash memory erase and write we have to give a fixed sequence of commands i.e. fixed values on address and data bus both. In burst mode we can send the fixed values on data bus, but not on address bus. So we need to hold the same data for 8 clock cycles to give one command in the required sequence. That will bring down the throughput of the system.

So, we are finding a possibility to stop the burst immediately after the first data so that the transaction is complete in just 1 cycle instead of 8 cycles. Th user guide says we can stop the burst by issuing a BT command. I want to know whether or not the OMAP can control this and how and not what condition a BT command can be issued.

You said "SDRAM controller operates autonomously". By this I understand that internally the SDRAM controller will take decisions like whether to issue a precharge or not (comparing the row addresses) etc. I want to know if there is anything in the user's control to force a command like Burst Terminate, Precharge Load Mode Register etc., to the SDRAM controller.

Hope the requirement is quite clear. Your reply will be appreciated as soon as possible.

-Ashlesha

Ashlesha Raut said:

The requirement is to connect SRAM and Flash memories to EMIFB bus via a FPGA.

SRAM and Flash are async interfaces which are only supported on EMIFA.  The concept of pages, refresh, etc. do not apply to SRAM and Flash.

Ashlesha Raut said:

Hope the requirement is quite clear. Your reply will be appreciated as soon as possible.

I'm even more confused at what you're asking and trying to do.  I think you need to change your architecture to utilize EMIFA for this purpose.