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EDMA access for multiple GPMC channels

sweta bhatt
Expert 2345 points
Other Parts Discussed in Thread: OMAPL138, TMS320C6748

Hi,

We are developing an Integra based product.

NAND will be interfaced on Chip select 0. On Chip select 1, we'll have a memory mapped device (Slave processor's interface).

As I understand from datasheet, there is only one EDMA channel for GPMC interface (Channel : 52)

Questions:

1) Does EDMA driver support data xfer events from multiple requests from same channel ID ? Will data be consistent and intact, if both NAND and memory mapped device start initiate transfer simultaneously ?

If no, does NAND driver (drivers/mtd/nand/omap2.c) and interface driver for mem. mapped device need to take care before initiating xfer ?

2) From where can I get register level details and detailed information about EDMA ? EDMA user guide from ezsdk_5_00_11 doesn't have sufficient information.

Is this EDMA3 similar to the one used in TMS320C6748/46/42/OMAPL138?

Thanks,
Sweta