c6678 PLL configuration

Additionally, we will need to configure the PLLs for the EMAC and SRIO interfaces. From the datasheet, they both use the same clock input, which we have set to 156.25 Mhz. The SRIO user guide states thet the clock should be set to 1/10th or 1/20th of the desired line speed. We plan to run at 2.5 Ghz. I haven't looked into the PLL settings yet, but if you could provide them, that would be appreciated.

I'm not clear on how to set the EMAC PLL. The EMAC guide doesn't specifically state what speed the clock should be set to, but it seems to imply that the clock should be multiplied up to the desired SGMII line speed. Is this correct? Also, the GbE subsystem guide (SPRUGV9) points to the device specific datasheet for all of the SGMII SERDES register offsets, but I do not see SGMII or EMAC registers listed in the C6678 datasheet memory map. Can you please provide the offset for these registers.

 Aditya,

 It looks like we set our register values correctly and  should be running at 1Ghz. We did use table 2-13 to figure this out, but it's a bit confusing when looking at the block diagram and registers.

 If you look at figure 7-23, and section 7.8.1.1, REFCLK should be the full rate clock for the core pac. This should be 1000Mhz. We have a test pad on SYSCLKOUT, which is generated from SYSCLK7, which is 1/6 the speed of the output of the PLL. With the values listed above, we see about 158Mhz on SYSCLKOUT, which equates to 1000Mhz, BUT, from figure 7-23, this would be divided by 2 to generate the REFCLK, meaning that the REFCLK would really be set to 500Mhz. Is the figure incorrect?

 Above, you do not mention how SECCTL should be set. The description of this register is not clear. On the EVM, this is set to 0x00090000, which would suggest an output divide of 2. We can change this value and see the SYSCLKOUT change. What is this divider controlling?

 From the PLL manual, it appears there is a pre-divider and a post-divider. From what I can tell, the MAINPLLCTL0 register controls the pre-divider and the SECCTL controls the post divider, but based on our settings, I'm not sure how that works as we get the following:

 CLK = CLKIN X (PLLM+1)/(2X(PLLD+1))

 CLK = (156.25 X 64) / (2X5) = 1000 Mhz

 So, this accounts for the  Pre-divider, Multiplier, and divide by 2 for the REFCLK, but it still seems we have an extra divide by 2 in the path.

 When the DSP is running at 1Ghz, what should the frequency of SYSCLKOUT be? I would expect it to be 333.33Mhz for a DSP running at 1000Mhz, but that doesn't seem to be the case with the EVM.

Bryan,

The SRIO PLL settings needed for a 156.25Mhz reference and 2.5GBaud operation are described in the SRIO users guide:

http://focus.ti.com/lit/ug/sprugw1/sprugw1.pdf

Table 2-7.  It requires MPY setting in the CFGPLL register, as well as RATE settings in the CFGTX/RX registers.

Regards,

Travis

r_robotics,

The /2 divider should actually be /1 so REFCLK should be the same as PLL output. We will update the documentation to reflect that. This confirms what you see on SYSCLK7 is correct.

SECCTL should be set to the same value as in the GEL i.e. 0x00090000. This sets the output divider of the Main PLL to /2. Setting this to /2 is not necessary, but it is a good practice to reduce the jitter on the clock. This /2 in the SECCTL is compensated for by programming twice the value of multiplier in PLLM.

I am modifying the equation as follows:

CLK = CLKIN x (PLLM+1)/ (OUTPUT_DIVIDER x (PLLD+1))

For example, if you set output divider in SECCTL to 0x1, you should program PLLM = 31.

You will get CLK = 156.25 x (31+1)/(1 x 5) = 1000MHz.

If you program output divider = 2 (ie. SECCTL = 0x00090000), you should use PLLM = 2*32-1 = 63.

You will get CLK = 156.25 x (63+1)/(2 x 5) = 1000MHz.

We will update the figure 7-23 to include PLLD, OUTPUT_DIVIDER and PLLM at the appropriate places to give a clear picture and avoid further confusion.

Let me know if you have more questions.

Aditya,

 Thanks, this makes sense now.

 I think you should add a note that the values in Table 2-13 depend on SECCTL being set to 0x00090000 or that the output divider needs to be set to 2 for those values to be valid.

Bryan, yes that will be addressed as well.

Were you'll able to get 1000MHz  with the recommended register settings instead of the earlier 937MHz?

Aditya,

 Yes, we got the frequency to be 1000Mhz with hard coding the registers.

 The GEL file has a line where you can tell it what the input frequency to the part is in kHz and it will calculate all of the values using the equations you listed above. The problem is that for a multiplier of 63 and a divider of 4, you get 6.4 out of the equation above. The math in the GEL file simply rounds this to 6 and that is what was giving us the frequency of 937Mhz.

Bryan,

Okay. Good to know you have it running at 1GHz. I have contacted the EMAC/SGMII owner to respond to your concerns on the PLL and registers.

Travis,

 Got it. What is the VRANGE bit used for?

 I also see some mistakes in the RX and TX registers. Not sure if this is the right place to bring this up or if I should start a new post, but in the SRIO_SERDES_CFGRX register, I see the following:

bits 20 - 18 = EQ  The EQ is specified as a 4 bit field, but there are only 3 bits specified in the register definition. 4 bits appear to be correct based on table 2-10, but which 4 bits is it? 21 - 18 or 20 -17?

bits 14 - 12 = LOS. This implies a 3 bit field, but the description only shows 2 bits.

My best guess is that 13 - 12 = LOS, 16 - 14 = CDR, and 20 - 17 = EQ.

Also, Table 2-10 shows the EQ bits as 22 - 19 and table 2-11 shows the Loopback bits as 28 - 27

SERDES_CFGTX0_CNTRL

bits 18 - 14 = TWPST1, this implies a 5 bit field but only 4 bits are shown in the description.

bits 10 - 7 - SWING, this implies a 4 bit field, but only 3 bits are used in the description.

Table 2-13 shows that SWING is 4 bits, but specifies bits 12 - 9

Table 2-14 shows TWPRE as bits 15 - 13

Table 2-15 shows TWPST1 as bits 20 - 16

Table 2-16 shows loopback as bits 28-27

Please clarify what bits are what in these registers. I don't think we will need to change them from the EVM settings, but we may. Regardless, that section needs to be fixed.

Also, what are the default or recommended values for the registers?

The Ethernet subsystem registers are part of the PA subsystem configuration space. They start at base address = 0x02090000. I will let the EMAC owner comment on the PLL.

Bryan,

For VRANGE, if LINERATE × RATESCALE < 2.17GHz, VRANGE should be set high.

With regards to documentation errors, always feel free to submit via the "submit documentation feedback" hyperlink at the bottom of the document pages.  I'll get these submitted, if they haven't been submitted already.

The figures in http://focus.ti.com/lit/ug/sprugw1/sprugw1.pdf for these registers ARE correct, except for Figure 2-7 (cfgtx) which is missing MSYNC at bit 20.

EQ is 3 bits, bits 20-18.  Just leave it at 0b001 and you will be fine.  Table 2-10 is completely wrong, and will be fixed.

LOS is 3 bits, bits 14-12.  Leave it disabled 0b000. Will update Table 2-9.

Table 2-11 and 2-16 will be updated with the correct loopback bits called out.

TWPST1 = 5bits, bits 18 -14

SWING = 4 bits, bits 10 -7

If you use the SRIO LLD example provided in the PDK, they should be setup for you.

http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html

Regards,

Travis

Several of our programs are getting hung in PLL initialization.  As a check we ran the stock "client" NDK demo on our eval boards.  Every time, the program hangs by looping through these lines:

while (loopCount--) {

       asm("      NOP");

}

/*set pprst to 0 to deassert pll reset */

ctl = ctl & ~(1<<3);

(at this point the program jumps back to the assembly line) and keeps looping.  For what it's worth, the same exact code executes flawlessly in other programs.  Any idea what could be culprit?

Thanks!

Bryan,

The SGMII SERDES registers can be found at the following addresses. I have contacted the owner of the data manual and these addresses will be in the data manual in the next release.

0x02620158 - SGMII_SERDES_STS

0x02620340 - SGMII_SERDES_CFGPLL

0x02620344 - SGMII_SERDES_CFGRX0

0x02620348 - SGMII_SERDES_CFGTX0

0x0262034C - SGMII_SERDES_CFGRX1

0x02620350 - SGMII_SERDES_CFGTX1

When configuring the SGMII SERDES PLL, the it should be configured to 1.25 times the desired data rate. Due to 8b/10b encoding, the efficiency of the SGMII SERDES interface is reduced to 80%. To compensate for this, you need to operate the SERDES at 10/8 or 1.25 times the line rate that you would like to operate at.

Line rate 1000 MHz, SERDES rate 1250 MHz

Line rate 100  MHz, SERDES rate 125  MHz

Line rate 10   MHz, SERDES rate 12.5 MHz

In the previous email, you said that you want to use 156.25 MHz for your reference clock. Assuming that you are operating at a linerate of 1000 MHz, then you want to operate the SGMII SERDES at 1250 MHz. If you multiply your reference clock of 156.25 by 8, then it will give you the desired 1250 MHz. To acheive this set the MPY field to 7'b0100000. Then set the ENPLL bit to 1 to enable the SGMII SERDES PLL. 

To acheive this configuration, set the SGMII PLL Configuration Register as shown below:

SGMII_SERDES_CFGPLL = 0x00000041;

Please let me know if this is not clear, or if you have any additional questions.

Regards,

Derek

r_robotics, can you start a new thread on this issue? It will be easier for forum users to track.

Absolutely, here's the link:

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/118515/421458.aspx#421458

Thanks!