Part Number: AM3352
Hi team,
Here're some questions from the customer may need your help:
1) The serial interface uses the FIFO DMA to transmit and receive data of 10 bytes per frame. The FIFO uses the following configuration. But no data is received on the serial interface.
fifoConfig = UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_1,
UART_TRIG_LVL_GRANULARITY_1,
10,
10,
1,
1,
UART_DMA_EN_PATH_SCR,
UART_DMA_MODE_1_ENABLE);
/* Configuring the FIFO settings. */
UARTFIFOConfig(baseAdd, fifoConfig);
The function to determine if the serial interface is receiving data is complete is as follows:
while((HWREG(reg + UART_RXFLL)&0xFF) == 10)
{
paramType->RxFlag = 1;
paramType->Root.Buffer[num][len++] = UARTCharGetNonBlocking(reg);
paramType->Root.Clen[num]++;
}
How to configure it?
2) Could you help specify the 19.3.6.4.1 DMA transfers (DMA Mode 1, 2, or 3) in the Technical Reference Manual?
3) Can the FIFO and DMA modes be used individually or together?
4) What is the data storage address in the receive and transmit FIFOs in a debug environment?
5) What is the DMA mode storage address in a debug environment?
6) What is the difference in UART mode in 3 of MODESELECT of MDR1?
7) Is there only 3 ways for the serial port transceiver configuration? What are the judging flags for each?
a. Enable DMA mode0 individually, with FIFO_EN = 0, data between DMA and RHR, thr one byte at a time. Is it true that the data transmit and receive flags are LSR bit4, bit5, and bit0?
b. Separate FIFO UART_SCR[0] DMA_mode_CTL = 1, UART_SCR[2:1]DMA_mode_2 = 0, what is the judgment flag bit?
c. DMA and FIFO are used together, and data is transferred to the FIFO before the DMA. How is each phase triggered and what is the judging flag?
Could you help check this case? Thanks.
Best Regards,
Cherry
