AM6442: TMDS64GPEVM

Hello zhang ben,

I am not a Linux expert but will share information on how to route your GPIO interrupts to A53 core.

We have already created a FAQ on routing GPIO interrupts and please go through it and it will be helpful.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1123825/faq-am6442-how-to-configure-the-gpio-interrupt

According to TRM, GPIO interrupts are routed to the GIC A53 core and the router output is 0 to 15.

Then, you can go through the link below and open the scilient_defaultBoardcfg_rm .c file and

 C:\ti\mcu_plus_sdk_am64x_08_04_00_17\source\drivers\sciclient\sciclient_default_boardcfg\am64x_am243x now  

{
.num_resource = 8,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_2,
},

According to the software you need to configure the router output as 0 to 7 and destination ID as A53 core.

You have already an example of GPIO interrupt on R53 and now you can make changes for A53 with update Router ID and Destination core.

Regards,

S.Anil.

Hello Anil,

Thanks for your reply!

Based on your suggestions, I made the following tests.

Step1: Put the Interrupt router output as 0 to 7 and destination core is A53FSS_0., put the Interrupt router output as 8 or 9 and destination core is R5FSS_0.

{
.num_resource = 8,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_0,
},
{
.num_resource = 2,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 8,
.host_id = TISCI_HOST_ID_MAIN_0_R5_0,
},

Step2: R5 calls the function Sciclient_boardCfgRm configures interrupt routing.

    if (SystemP_SUCCESS == status)
    {
//        static uint8_t boardCfgLow[] = SCICLIENT_BOARDCFG_RM;
        Sciclient_BoardCfgPrms_t boardCfgPrms_rm =
        {
            .boardConfigLow = (uint32_t)&gBoardConfigLow_rm,
            .boardConfigHigh = 0,
            .boardConfigSize = sizeof(struct tisci_local_rm_boardcfg),//SCICLIENT_BOARDCFG_RM_SIZE_IN_BYTES,
            .devGrp = DEVGRP_ALL,
        };
        status = Sciclient_boardCfgRm(&boardCfgPrms_rm);
        if (SystemP_SUCCESS == status)
        {
        	printk("[SCICLIENT] RM Board Configuration PASSED \r\n");
        }
        else
        {
        	printk("[SCICLIENT] RM Board Configuration has failed \r\n");
        }
    }

[sciclient_set_boardcfg, 170]
[SCICLIENT] ABI check PASSED 
[SCICLIENT] Board Configuration with Debug enabled ...
[SCICLIENT] Common Board Configuration PASSED 
[SCICLIENT] PM Board Configuration PASSED 
[SCICLIENT] RM Board Configuration PASSED 
[SCICLIENT] Security Board Configuration PASSED 
All tests have passed!!

Step3:Configure interrupt routing for GPIO1_43.

I did two tests, the first time to route to R5_00 and the second time to route to A53_0.

GPIO1_43 interrupt  route to R5_00(AMP)：

#define BOARD_BUTTON_GPIO_INTR_NUM      (40U)

#define TISCI_BANK_SRC_IDX_BASE_GPIO1       (90U)

#define GPIO_PUSH_BUTTON_PIN (43)

#define GPIO_PINS_PER_BANK_SHIFT        (4U)
#define GPIO_GET_BANK_INDEX(pinNum)     (((uint32_t) pinNum) >> GPIO_PINS_PER_BANK_SHIFT)

#define MAIN_GPIOMUX_INTROUTER0_OUTP_8                                      (40U)
uint32_t Sciclient_gpioIrqSet(void)
{
    int32_t                             retVal;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = TISCI_DEV_GPIO1;
    rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);
    rmIrqReq.dst_id                 = TISCI_DEV_A53SS0_CORE_0;
    rmIrqReq.dst_host_irq           = MAIN_GPIOMUX_INTROUTER0_OUTP_8;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
    if(0 != retVal)
    {
        printk("[Error] Sciclient event config failed!!!\n");
    }

    return retVal;
}

[sciclient_set_boardcfg, 170]
[SCICLIENT] ABI check PASSED
[SCICLIENT] Board Configuration with Debug enabled ...
[SCICLIENT] Common Board Configuration PASSED
[SCICLIENT] PM Board Configuration PASSED
[SCICLIENT] RM Board Configuration PASSED
[SCICLIENT] Security Board Configuration PASSED
All tests have passed!!
[sciclient_set_boardcfg, 279]
[Error] Sciclient event config failed!!!

GPIO1_43 interrupt route to A53_0(AMP)：Board Configuration at R5_00, but GPIO demo runs on A53_Core0.

#define BOARD_BUTTON_GPIO_INTR_NUM      (32U)

#define BOARD_BUTTON_GPIO_INTR_NUM      (32U)

uint32_t Sciclient_gpioIrqSet(void)
{
    int32_t                             retVal;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = TISCI_DEV_GPIO1;
    rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);
    rmIrqReq.dst_id                 = TISCI_DEV_A53SS0_CORE_0;
    rmIrqReq.dst_host_irq           = getGpioButtonIntrNum();
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);
    if(0 != retVal)
    {
        printf("[Error] Sciclient event config failed!!!\n");
    }

    return retVal;
}

[ERROR]Invalid cpu_brandstr AM64x Cortex-A53/1 @ 1.00GHz.
This A53_Core0
[Error] Sciclient event config failed!!!
This A53_Core0

Thanks.

Zhang Ben

Could you please provide some use caces for me? Which can successfully route GPIO1_ 43 interrupt to A53_ 0 and R5. The image can be programmed to and booted from OSPI flash memory.

Hello ,

MCU + SDK 8.4 version has GPIO interrupt example routing interrupt to R5F0_0 and you need to load binaries on R5F0_0 and routing interrupt to A53 core has no example. Same GPIO interrupt example can be routed to other R5F cores. The router output should be updated. I understand that you want to route  the GPIO1_43 interrupt to A53 core. Please give me 1 or two days to share the example code.

I hope you can route  GPIO1_43 pin interrupt to R5F0_0 and you are having problem while routing pin interrupt to A53 core.

Please configure GPIO1_43 pin interrupt to A53_1 core instead of A53_0 and let me know if you face issue .

Regards,

S.Anil.

Hello,Anil

OK, thank you very much and look forward to your reply.

We have used MCU + SDK 8.4 version GPIO interrupt example and testing with jtag(NOBOOT MODE，loading syfw.bin with script). It can work successfully.

However, if the gpio_ input_ interrupt_ am64x-evm_ r5fss0-0_ nortos_ ti-arm-clang. out file is programmed into OSPI Flash and boot from OSPI flash(setenv serverip 192.168.1.101;setenv ipaddr 192.168.1.100;tftpboot 0x82000000 gpio_ input_ interrupt_ am64x-evm_ r5fss0-0_ nortos_ ti-arm-clang. out;sf probe;sf update 0x82000000 0x280000 0x2c0000), the instance cannot run normally.Maybe you can do the same test to see if the phenomenon is the same as me.

The customer requested that we only use A53 core0.

Thanks

Zhang Ben

zhang ben said:

However, if the gpio_ input_ interrupt_ am64x-evm_ r5fss0-0_ nortos_ ti-arm-clang. out file is programmed into OSPI Flash and boot from OSPI flash(setenv serverip 192.168.1.101;setenv ipaddr 192.168.1.100;tftpboot 0x82000000 gpio_ input_ interrupt_ am64x-evm_ r5fss0-0_ nortos_ ti-arm-clang. out;sf probe;sf update 0x82000000 0x280000 0x2c0000), the instance cannot run normally.Maybe you can do the same test to see if the phenomenon is the same as me

Hello zhang ben ,

Sure I can update the status after testing the GPIO interrupt example on my end and let you know.

As mentioned earlier I am not a Linux expert but I will try to test the GPIO interrupt example on my end with version 8.4 +MCU+SDK in OSPI boot mode.

I hope it works and we'll see.

zhang ben said:

The customer requested that we only use A53 core0.

According to the Scilient_default_boardcfg file all GPIO interrupts are routed to the A53_1 core only. So, you can't edit Scilient_default_boardcfg  file now and I need to check if there is any other possibility to route GPIO interrupts to A53_0 core

 C:\ti\mcu_plus_sdk_am64x_08_04_00_17\source\drivers\sciclient\sciclient_default_boardcfg\am64x_am243x now  

{
.num_resource = 8,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_2,
},

Regards,

S.Anil.

Hello Anil.

Would you kindly inform me of the progress on？

Swargam Anil said:

Sure I can update the status after testing the GPIO interrupt example on my end and let you know.

As mentioned earlier I am not a Linux expert but I will try to test the GPIO interrupt example on my end with version 8.4 +MCU+SDK in OSPI boot mode.

I hope it works and we'll see

Hello zhang ben ,

I verified the GPIO interrupt with my HW and it is working fine.

May I know if you are running the example on RTOS or Linux?

I verified GPIO interrupt example in RTOS and MCU + SDK 8.4 version.

Regards,

S.Anil

Hello Anil,

We are running the example On RTOS with TMDS64GPEVM.

Can I find out what boot mode you are using? Because if we use NOBOOT MODE, load binaries from css, it is working fine. But if we boot

 from flash , without "loadJSFile "D:\project\CVC300\ti\mcu_plus_sdk_am64x_08_02_00_31\tools\ccs_load\am64x\load_dmsc.js"",there is something wrong.

Could you please give your code ?

Thanks,

Zhang Ben

Hello zhang ben,

I took the example from the MCU+SDK documentation and tested it on my HW. I loaded the GPIO interrupt example into external memory and tested it. It is working well.

So, you can take the same example from below link.

C:\ti\mcu_plus_sdk_am64x_08_04_00_17\examples\drivers\gpio\gpio_input_interrupt\am64x-evm

I suspect a problem with your flashing procedure.

Generally we have to follow below procedure to load binaries in external memory.

Pre condition : 

1. Open default_sbl_ospi.cfg file from below path.

C:\ti\mcu_plus_sdk_am64x_08_04_00_17\tools\boot\sbl_prebuilt\am64x-evm

2. Give the path of GPIO interrupt example appimage in place marked yellow.

.

Procedure :

1. POWER OFF
2. Put the board in UART BOOT MODE
3. Open the following path and open a command prompt window, then you give the below command.

C:\ti\mcu_plus_sdk_am64x_08_04_00_17\tools\boot

Command : python uart_uniflash.py -p COM8 --cfg=sbl_prebuilt/am64x-evm/default_sbl_ospi.cfg

Note : Pease change the com port number based on your USB port number.

4. Wait for App image transfer via UART and put the board in OSPI BOOT MODE

5. POWER ON

Please let me know if you face any problem .

Regards,

S.Anil.

Hello Anil,

I tested it on my TMDS64GPEVM board, it is working well.Could you please yell me ,what files constitute appimage? In other words, what are the differences between appimage and .out files.

My customer has customized a board with AM64x chip and used the boot of linux sdk0802. In the future, it will switch to linux sdk0804 and boot our own RTOS through uboot.

We porting the GPIO, sciclient and other drivers of the sdk to our RTOS bsp, but we were unable to configure GPIO interrupt.Except for the GPIO interrupt, other drivers work well.So,how to configure GPIO interrupt routing in our own RTOS through sciclient.

Sorry, my expression and my English may not be very good.

Thanks,

Zhang Ben

Hello zhang ben,

Don't worry about your English. I can ask you if I can't understand your language. No problem there.
Please raise threads if you have any problems.
Apart from this normally when you load your application from CCS you need .out file and load application in external memory or sd card , you need app image file.
These two files are available after compiling your application.

Please find those files with link and image below.

C:\Users\......\empty_am64x-evm_r5fss0-0_freertos_ti-arm-clang\Debug

Based on your inputs I understand that the customer is using his own HW with AM64X SOC, SD boot mode and 8.2 SDK version.

Could you please provide the details below?

1. Which boot mode are you using?

2. Which GPIO pin do you want to enable the GPIO interrupt

3. You want to use GPIO interrupt on core R5F0_0 or R5F0_1 or R5F_1_0 or R5F1_1 or MCU M4 

Regards,

S.Anil.

Hello Anil,

1. OSPI BOOT MODE

2. PIN_GPIO0_7、PIN_GPIO0_8、PIN_GPIO0_9、PIN_GPIO0_10、PIN_GPIO1_0、PIN_GPIO1_1、PIN_GPIO1_2、PIN_GPIO1_3、PIN_GPIO1_5、PIN_GPIO1_6、PIN_GPIO1_7、PIN_GPIO1_21、PIN_GPIO1_28、PIN_GPIO1_43

3. In fact, I want to use GPIO interrupt on A53SS0_CORE_0 only.

We found that after converting our own RTOS binaries(.obj file) to appimage file,Sciclient_rmIrqSet returned success,but still did not generate a GPIO interrupt.

We will continue to try more, and we will keep you informed if there is progress, thank you for your help.

Thanks,

Zhang Ben.

Hello zhang ben, 

According to the Scilient_default_boardcfg file all GPIO interrupts are routed to the A53_1 core only. So, you can't edit Scilient_default_boardcfg  file now and I need to check if there is any other possibility to route GPIO interrupts to A53_0 core

 C:\ti\mcu_plus_sdk_am64x_08_04_00_17\source\drivers\sciclient\sciclient_default_boardcfg\am64x_am243x 

{
.num_resource = 8,
.type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
.start_resource = 0,
.host_id = TISCI_HOST_ID_A53_2,
},

zhang ben said:

3. In fact, I want to use GPIO interrupt on A53SS0_CORE_0 only.

I need to spend time to create example on GPIO interrupt in A53_0 core and please give me some time to get back you.

Regards,

S.Anil.

Hello Anil,

I am looking forward to you reply.

Merry Christmas in advance!

Thanks,

Zhang Ben.

Hello zhang ben, 

Merry Christmas and Happy New Year in advance.

I will try to post a reply next week as there is no example on MCU+SDK of GPO interrupt on A530 core.

Regards,

S.Anil.

Hello Anil,

Happy New Year.

Is there any progress on GPIO interrupt route to A53core0。

Thanks，

Zhang Ben.

Hello Zhang,

I will be helping you for now.

1) Please clarify what is generating the interrupt, and what is receiving the interrupt.
for example:
R5 generating an interrupt to A53?
Main domain GPIO module generating an interrupt to the A53?
MCU domain GPIO module generating an interrupt to the R5?

2) Please note that only a single core can configure a specific interrupt router. For example, as of Linux SDK 8.5 and earlier, the MCU domain GPIO interrupt router is defined in the Linux device tree (and thus enabled by default), but never disabled. So if you do not follow the steps in this "Attention" banner, then the MCU+ interrupt example will not work while Linux is running because multiple cores are trying to configure the same interrupt router: https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_04_00_17/exports/docs/api_guide_am64x/EXAMPLES_DRIVERS_GPIO_INPUT_INTERRUPT.html

So what does that mean? The core that is using the interrupt router should be the one to configure it. If you are configuring an interrupt between Linux and a GPIO module, the interrupt router should NOT be configured by the R5.

Regards,

Nick

Hello Nick,

We are configuring an interrupt between Linux(or our own RTOS) and a GPIO module.Main domain GPIO module generating an interrupt to the A53 Core0.

How to ensure that R5 is not configured with interrupt router in the sbl_ospi_linux?We only want to use GPIO interrupt on A53 Core0.

My colleagues are also tracking this issue.
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1185471/am6442-sbl_ospi_linux-cannot-run-gpio_input_interrupt-demo-on-am64x-evm-gp-board

Thanks,

Zhang Ben.

Hello Zhang,

Ok, let's break this question into parts.

1) How to make sure R5F is NOT using an interrupt router / peripheral? I will reassign your thread to Anil to comment.

2) How to configure Linux to use a GPIO module, including how to configure the interrupt from the GPIO router? Once we know R5F is not trying to use the GPIO, then Anil can reassign to the Linux owner to comment.

Regards,

Nick

Hello Nick,

Thanks for your help,  please let Anil help me with these two questions.

1) How to make sure R5F is NOT using an interrupt router / peripheral?

2) How to configure Linux to use a GPIO module, including how to configure the interrupt from the GPIO router? Once we know R5F is not trying to use the GPIO.

Thanks,

Zhang Ben.

Hello Zhang ben,

I have proposed a method to disable GPIO interrupts on the R5F, but I need to check with our design team and confirm with you before proceeding with this approach.

Please allow a day or two to contact you.

Meanwhile please go through the thread below and I hope it will be helpful.

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1185701/mcu-plus-sdk-am243x-using-mcu_gpio0_x-in-r5-gpio_input_interrupt-example

Regards,

S.Anil.

Hello Anil,

This is helpful, and we will test against those threads.

Spring Festival is coming, I will have a holiday after tomorrow, and I will reply to you after the holiday, thank you for your help.

Regards and Thanks.

Zhang Ben.

Hello Zhang ben,

I will reply as soon as possible .

Regards,

S.Anil.

Hello Anil,

How is it going?

Regards,

Zhang Ben

Hello Anil,

Yes,we are using OSPI_Linux.

This is very helpful. RM resource can only be allocated in SBL？

Thanks,

Zhang Ben.

Hi Prashant,

Thank you very much, so this is a one-time configuration, which must be linked to the image in the form of ". boardcfg_data" section.(The answer is in the function comment)

/**
 *  \brief  One time board configuration to be done from R5 for RM .
 *          User needs to define a section ".boardcfg_data" in the
 *          linker file for the default configuration, which needs to be present
 *          in OCMRAM . If user provides custom board_cfg, then the data must
 *          be present on OCMRAM.
 *
 *  \param pInPrms        [IN]  Pointer to \#Sciclient_BoardCfgPrms_t . NULL
 *                          results in default config.
 *
 *  \return SystemP_SUCCESS on success, else failure .
 *
 *
 */
int32_t Sciclient_boardCfgRm(const Sciclient_BoardCfgPrms_t * pInPrms);

Thank you for the reminder.

Regards,

Zhang Ben.

Hello Anil,

Using the rm_linux.c file you provided, we successfully triggered the GPIO interrupt on R5_00. Can you provide another instance of routing to A53 Core0? We have previously tried to modify this rm configuration ourselves, but failed.

/*
 * K3 System Firmware Resource Management Configuration Data
 * Auto generated from K3 Resource Partitioning tool
 *
 * Copyright (c) 2018-2022, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/**
 *  \file sciclient_defaultBoardcfg_rm.c
 *
 *  \brief File containing the rm boardcfg default data structure to
 *      send TISCI_MSG_BOARD_CONFIG_RM message.
 *
 */
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <drivers/sciclient.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_hosts.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_boardcfg_constraints.h>
#include <drivers/sciclient/include/tisci/am64x_am243x/tisci_devices.h>

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/* \brief Structure to hold the RM board configuration */
struct tisci_local_rm_boardcfg {
    struct tisci_boardcfg_rm      rm_boardcfg;
    /**< Board configuration parameter */
    struct tisci_boardcfg_rm_resasg_entry resasg_entries[TISCI_RESASG_ENTRIES_MAX];
    /**< Resource assignment entries */
};

const struct tisci_local_rm_boardcfg gBoardConfigLow_rm
__attribute__(( aligned(128), section(".boardcfg_data") )) =
{
    .rm_boardcfg = {
        .rev = {
            .tisci_boardcfg_abi_maj = TISCI_BOARDCFG_RM_ABI_MAJ_VALUE,
            .tisci_boardcfg_abi_min = TISCI_BOARDCFG_RM_ABI_MIN_VALUE,
        },
        .host_cfg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
                .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_host_cfg),
            },
            .host_cfg_entries = {
                {
                    .host_id = TISCI_HOST_ID_A53_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_M4_0,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
                {
                    .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
                    .allowed_atype = 0b101010,
                    .allowed_qos   = 0xAAAA,
                    .allowed_orderid = 0xAAAAAAAA,
                    .allowed_priority = 0xAAAA,
                    .allowed_sched_priority = 0xAA
                },
            },
        },
        .resasg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
                .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
            },
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        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
            .start_resource = 40,
            .host_id = TISCI_HOST_ID_A53_2,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_A53_2,
        },
        {
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
            .start_resource = 40,
            .host_id = TISCI_HOST_ID_A53_2,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
            .start_resource = 21,
            .host_id = TISCI_HOST_ID_A53_2,
        },
        {
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
            .start_resource = 48,
            .host_id = TISCI_HOST_ID_A53_2,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
            .start_resource = 25,
            .host_id = TISCI_HOST_ID_A53_2,
        },
        {
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
            .start_resource = 112,
            .host_id = TISCI_HOST_ID_A53_2,
        },
        {
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
            .start_resource = 0,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
            .start_resource = 2,
            .host_id = TISCI_HOST_ID_A53_2,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 20,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 22,
            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 24,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
        },
        {
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 26,
            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
        },
        {
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
            .start_resource = 28,
            .host_id = TISCI_HOST_ID_ALL,
        },
    }
};

Only A53 core0 is configured with GPIO interrupt router.

#define TISCI_BANK_SRC_IDX_BASE_GPIO0       (80U)
#define TISCI_BANK_SRC_IDX_BASE_GPIO1       (90U)
//#define TISCI_BANK_SRC_IDX_BASE_MCU_GPIO0   (90U)

#define GPIO_PUSH_BUTTON_BASE_ADDR (CSL_GPIO1_BASE)
#define GPIO_PUSH_BUTTON_PIN (42)
#define GPIO_PUSH_BUTTON_DIR (GPIO_DIRECTION_INPUT)
#define GPIO_PUSH_BUTTON_TRIG_TYPE (GPIO_TRIG_TYPE_RISE_EDGE)

#define MAIN_GPIOMUX_INTROUTER0_OUTP_0                             (32U)

DRV_UINT32 Drv_Sciclient_F_GpioIrqSet(DRV_VOID)
{
    DRV_INT32                             retVal;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = TISCI_DEV_GPIO1;
    rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO1 + GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);
    rmIrqReq.dst_id                 = TISCI_DEV_A53SS0_CORE_0;
    rmIrqReq.dst_host_irq           = MAIN_GPIOMUX_INTROUTER0_OUTP_0;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, WAIT_FOREVER);
    if(0 != retVal)
    {
    	debug_printf("[Error] Sciclient event config failed!!!\n");
    }

    return retVal;
}

Thanks,

Zhang Ben.

Hello Anil,

I have realized that the hostID corresponding to A53 Core0 is HOST_ID_A53_2.

But why does it fail to call Sciclient_rmIrqSet with A53 core0 using the file you provided.

Zhang Ben.

Hello zhang ben ,

May I know the issue is resolved or are you still facing the issue?

Regards,

S.Anil.

Hello Anil,

I'm afraid I still have a problem.

The Sciclient rmIrqSet function was successfully called with A53 core0.However, no interrupt is triggered.I'm trying to figure it out.

Thanks,

Zhang Ben.

Hello zhang ben ,

Yes I am also facing the same problem and please give some time and get back to you.

Regards,

S. Anil

Hello Anil,

Let's work together to solve this problem ! If I have any progress, I will give you feedback in time.

Thanks & Regards,

Zhang Ben.

Hello Anil,

I found a bug in .syscfg.This is auto-generated code, and the dst_id is wrong.

Regards,

Zhang Ben.

Hello zhang ben ,

We have also found this issue and will raise a Jira ticket to fix this issue in future releases.

Thanks for the update .

Regards,

S.Anil.

Hello Anil,

Thank you very much !

Yes, I know it can be set like this, but I think 0: Map interrupt as level interrupt, 1: Map interrupt as pulse interrupt.

Regards,

Zhang Ben.