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C645 - Disabling EMIF Command Re-ordering

aps
Prodigy 50 points

Hello All,

As per the TMS320C645x DSP External Memory Interface (EMIF) User's Guide, Section 7.1. The EMIF performs command reordering based on a set of rules. How can I disable this wholesale? Either for a specific area of program execution or for an entire chip select? Is there a pragma? Register? All of the above?

Thanks,

APS

  • 0
    TI__Guru* 84110 points

    The EMIF command reordering is not a user-controllable feature. Section 7.1 describes how the command reordering works and how it works to mitigate any problems.

    You can change the priority levels for different bus masters if you have a problem with one master starving out another too much.

    This reordering is intended to optimize performance, especially if you want a high-priority master like the CPU to not stall waiting for a read because of low-priority writes coming from another master.

    What problem do you have because of the command reordering, or are you just concerned with the possibilities?

  • 0 in reply to RandyP
    Prodigy 50 points

    The problem I am having with the command reordering is that I am using a flash device which requires specific sequence of commands, for example four consecutive writes to specific addresses and then a read(or reads). When I write the code to do this, the EMIF periphreal is moving the read in front of the write or writes, in which case I am reading back erroneous data because the proper command sequence is being violated.

    -aps

  • 0 in reply to aps
    TI__Guru* 84110 points

    For your case, it would be convenient to turn off the re-ordering.

    There is a work-around in spru971c Section 7.3 on page 35 that might work for you. It was written for the case of synchronizing two different masters, but should work for your case, too. Re-wording it for your situation, the new work-around would be:

    1. Perform the four consecutive writes to the Flash device.
    2. Perform a dummy write to the EMIF module ID and Revision Register (it is read-only, so this write is ignored).
    3. Perform a dummy read from the EMIF module ID and Revision Register (this will wait for the dummy write to finish).
    4. Do your Flash device read.

    The proper ordering should be retained. Does this look workable for your situation?