About the unused clock pin of C6678

haopeng han

SPRABI2 Page 15 has the recommended connections of the unused clock input pins for Keystone devices:

I want to know here which power rail is? Is it 1.0V? Since Bill Taboada says " You shouldn't start them before the 1V AVS is present because the clock buffers are powered by 1V." in http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/116580/413748.aspx#413748

Thanks in advance!

Han

over 14 years ago

0 Chad Courtney over 14 years ago

TI__Mastermind 30825 points

Han,

I believe it would depend on the clock. You'd want to use whichever rail the clock that is being unused would normally use. For LVDS Differential Clocks that would be 1.8V normally.

Best Regards,

Chad

0 Bill Taboada over 14 years ago in reply to Chad Courtney

TI__Mastermind 42545 points

Although 1.8V is within the acceptable voltage range of the input clock buffers they are internally supplied with the CVDD (core AVS) voltage. Since the clock buffers are not fail-safe they should not be driven before the CVDD voltage is present. Since the voltage sequencing allows 1.8V to be present before CVDD it's safer just to pull the unused clock p input to CVDD in all cases. Connecting the clock p input to CVDD and pulling the clock n input to ground through the resistor will hold the clock buffer in a stable state.

0 haopeng han over 14 years ago in reply to Bill Taboada

Expert 1120 points

Thank you for the prompt reply.

Han

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About the unused clock pin of C6678