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EDMA TMS320C6416

Mahdi SAKKA
Prodigy 120 points

Other Parts Discussed in Thread: TMS320C6416

Hi there,

I am using a TMS320C6416 DSK, it contains a 64 channel EDMA, I was wondering if I can use multiple channels of this EDMA at the same time to transfer data from source to destination addresses,if not how can I do transfers of data in a fast way so that I wouldn't require a waiting time

Thank you,

Sincerely,

  • 0
    TI__Intellectual 1305 points

    Hi,

    Yes, all the available EDMA channels can be configured and triggered to do the data transfer from source to destination memory at the same time. However, please check if any of the EDMA channels are used by the peripherals (like UART, McASP etc) in your system.

    Please go through the EDMA user guide for detailed information.

    http://focus.ti.com/lit/ug/spru234c/spru234c.pdf

    Regards,

    Nag

     

  • 0 in reply to Nagabhushan Reddy
    Prodigy 120 points

    Hi there,

    For Nag, did you mean that I should just select a different channel number for each transfert then trigger this transfert????

    Thank'a a lot

  • 0
    TI__Mastermind 18130 points

    Mahdi SAKKA said:
    I am using a TMS320C6416 DSK, it contains a 64 channel EDMA, I was wondering if I can use multiple channels of this EDMA at the same time to transfer data from source to destination addresses,if not how can I do transfers of data in a fast way so that I wouldn't require a waiting time

    The C6416 used the EDMA2 (as opposed to EDMA3 engine in the newer C64x+ parts) which was not capable of simultaneous transfers. EDMA2 had different priority levels to determine which transfer occurs next, but these different priority levels were not capable of operating simultaneously.

    You can configure multiple EDMA channels in such a way that they service the most important transfers first ("urgent" or "high" priority) and then the lesser important transfers later.

  • 0 in reply to TimHarron
    Prodigy 120 points

    Hi,

    So, EDMA in the C6416 DSK isn't capable to do simultaneous transfers, I will try to verify this thank you[:)]

  • 0 in reply to Mahdi SAKKA
    TI__Guru*** 125430 points

    Tim is correct that at any given time only one EDMA TC can be transferring data.  However, let's say we have the following scenario:

    * High priority TC transferring from L2 -> SDRAM

    * Low priority TC transferring from L2 -> L2

    In the above scenario the high priority TC is always given priority.  However, compared to internal memory SDRAM is slow.  During the "dead cycles" where the high priority TC is waiting for the EMIF to become ready the low priority TC is able to transfer data.

    So in this scenario some people might say that they are not simultaneously transferring data because at any given moment in time only one TC physically controls the bus.  However, a higher level perspective might consider this scenario as happening in parallel because the low priority TC does not have to wait for the entire high priority transfer to complete, so in that sense it is happening at the same time.

    By the way, if you have not read spra994 then I highly recommend it.  It gives a nice overview of the EDMA architecture that nicely compliments the user guide.  Since it is only 20 pages you might find it a bit easier to digest.

    Brad

  • 0 in reply to Brad Griffis
    Guru 13202 points

    Brad, if you might be monitoring this thread, could you please clarify my situation too?

    I use EDMA controller of C6416 to service FPGA transfers on EMIFA. I have pretty long receive (read) transfer, but for timing reasons I need relatively short transmit (write) transfer to occur somewhere during receive transfer. So, I have L2 -> EMIF A and L2 <- EMIF A transfers. Definitely, EMIF A is slower, then L2, so if I assign write transfer higher priority, will it take over reading transfer? Is it safe scheme to use?

    Thanks in advance.

     

  • 0 in reply to Victor Kazmirenko
    TI__Guru*** 125430 points

    Arbitration will occur in 2 places:

    1. At the EDMA.  You have correctly stated that if the L2 -> EDMA transfer is assigned higher priority then the EDMA will stop sending the data requests for EDMA <- L2.
    2. At the EMIF.  There are command queues in the EMIF that operate in FIFO order.  In particular see page 7 of spra994.  So in particular you'll see that EMIFA has a read buffer that is 4 commands deep, where each command contains up to 16 words (64 bytes) of data.

    So putting these 2 pieces of information together, the EDMA transfer controller will immediately send your write request for your higher priority transfer as soon as it's ready.  However, assuming the read transfer was already in progress there will already be 4 commands of 64 bytes each already queued up in the EMIF.  Therefore you will first see the 256 bytes from the lower priority read occur prior to any data associated with the higher priority write.

    Hopefully that 256 byte read delay isn't a big deal to your application (no way around it), in which case I expect this to be a safe mechanism to use.

  • 0 in reply to Brad Griffis
    Guru 13202 points

    Thanks for reference and clarification. That's what I want. 256 bytes on the background on kilobytes are minor issue.