• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 320 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Where is the EMIF register descriptions for C6A816x?

hutchman
Expert 1100 points


Hi,

I have the latest datasheet and sprug9 that I know of for the c6a816x.  I'm going through the GEL file for the DDR3 EVM trying to understand the EMIF0 and EMIF1 setup so I can make changes to my own custom DDR3 board that I'm trying to bring up.

The datasheet shows EMIF0 registers starting at 0x4c000000 but it is not obvious to me if any of the register definitions in the DMM section of sprug9 match up to this memory section since the offsets in the datasheet don't match.

I've also seen reference to an additional datasheet for DDR DMM but I can't find it.

Example:  The GEL file is writing to EMIF4_0_SDRAM_TIM_1 which is defined as being EMIF4_0_CFG_BASE_ADDR + 0x18.  EMIF4_0_CFG_BASE_ADDR = 0x4c000000 and I can't find a register description to figure out what is going on here.

Thanks,

Brian

 

  • 0
    TI__Mastermind 25055 points

    Brian,

    We are correcting the register offsets in the datasheet; the correct ones are: 0x4C000000 and 0x4D00000.

    We are also working to add the register details to the TRM, and plan to have this available soon.

    Regards,
    Marc

  • 0 in reply to MarcPyne
    Expert 1100 points

    Yes, our FAE sent me the preliminary DDR2_3.pdf and that helped a lot.

    Is there a separate DDR PHY spec too?

    Now I'm trying to find register descriptions for things like:

      WR_MEM_32(DDRPHY_CONFIG_BASE + 0x134, 1);
      WR_MEM_32(DDRPHY_CONFIG_BASE + 0x1d8, 1);
      WR_MEM_32(DDRPHY_CONFIG_BASE + 0x27c, 1);
      WR_MEM_32(DDRPHY_CONFIG_BASE + 0x320, 1);

    The datasheet says DDRPHY_CONFIG_BASE can be 0x48198000 or 0x4819a000 but I can't find any documentation that talks about what these address offsets are.

    Regards,

    Brian

     

  • 0 in reply to hutchman
    Prodigy 40 points

    hello~!  where  can  find  DDR2_3.pdf  ？  thank  ~

     

  • 0 in reply to li jack77472
    Expert 1100 points

    From what I understand you have to get it from your TI rep.  The file is DM816x_DDR2_3.pdf.  I'm also told that it is scheduled to go into the TRM (sprug9) sometime this month

    Regards,

    Brian