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How to check if the message is sent out using SRIO in C6455 EVM?

Renaissance
Intellectual 925 points

I created a srio_TX_message function as following. I upload the program to the EVM and I want to check if the message is successfully sent out.

From the spec, I expect the HDP will be reset to all 0s by the port and the ownership will also be set to be 0. But in the debug mode, I did not see the change. Can any of you give some suggestion?

Thanks a lot.

*****************************************************************************************

CSL_SrioBuffDesc tx_buffer_dec0;

void srio_TX_message(Uint32 dst, MessageInf msg)
{
 hSrio->regs->QUEUE_TXDMA_HDP[0] = 0;
 tx_buffer_dec0.buffPtr = (int )&msg;
 tx_buffer_dec0.nextDescPtr = 0;
 tx_buffer_dec0.opt1 = CSL_FMK(SRIO_TXBUFFDESC_DEST_ID, dst)|
        CSL_FMK(SRIO_TXBUFFDESC_PRI, 1)|
        CSL_FMK(SRIO_TXBUFFDESC_TT, 1)|
        CSL_FMK(SRIO_TXBUFFDESC_PORT_ID, 3)|
        CSL_FMK(SRIO_TXBUFFDESC_SSIZE, CSL_SRIO_TXBUFFDESC_SSIZE_256B)|
        CSL_FMK( SRIO_TXBUFFDESC_MAILBOX, 0);

 tx_buffer_dec0.opt2 = CSL_FMK( SRIO_TXBUFFDESC_SOP,1 )|
        CSL_FMK( SRIO_TXBUFFDESC_EOP,1 )|
        CSL_FMK( SRIO_TXBUFFDESC_OWNERSHIP,1 )|
        CSL_FMK( SRIO_TXBUFFDESC_EOQ,1 )|
        CSL_FMK( SRIO_TXBUFFDESC_TEARDOWN,0 )|
        CSL_FMK( SRIO_TXBUFFDESC_RETRY_COUNT,0 )|
        CSL_FMK( SRIO_TXBUFFDESC_CC,0 )|
        CSL_FMK( SRIO_TXBUFFDESC_MESSAGE_LENGTH,32 );


 hSrio->regs->QUEUE_TXDMA_HDP[0] = (Uint32)&tx_buffer_dec0;
}

  • 0
    TI__Guru* 84110 points

    You are reading the spec correctly. If "debug mode" means you are using CCS with breakpoints or single-stepping, this should not affect the correct operation of the SRIO peripheral.

    If the HDP is not reset to 0, then the operation has not completed. And that probably means that either there was an error (check the error register fields) or the operation was not properly started. Or the SRIO peripheral as a whole is not completely configured correctly.

    Hopefully, you can get a working Message example from the Community.

    Regards,
    RandyP

     

  • 0 in reply to RandyP
    TI__Mastermind 23525 points

    Agreed, the port should clear the HDP when it is done with ALL the descriptors in the TX queue.  The CP will be incremented when each TX descriptor is complete and the OWNERSHIP bit in the TX descriptor will be cleared.  So you could check those to see if it is completing each descriptor.  Also, if your interrupts are setup correctly, you should get an interrupt after each TX descriptor is complete. 

    Since you aren't seeing HDP being cleared, you may want to check one thing in your TX buffer descriptors to make sure that the peripheral actually knows that it has reached the last descriptor in the queue.  The peripheral hardware does not look at the EOQ bit in the TX descriptor, nor does it look at the OWNERSHIP bit, these bits are really for software to read/use and so they are set appropriately by the peripheral.  The peripheral will determine that it has reached the last buffer descriptor in a queue if the NEXT_BUFFER_DESCRIPTOR field is set to 0.

     

    Hope that helps,

    Travis