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Power-down Sequence Clarification

Russell Cumber
Prodigy 100 points
Other Parts Discussed in Thread: AM3517

I could use some clarification on the following section of the user manual. 

1 - Are there any voltage ramp limitations during power down?  

2 - In step 3, what is the tolerance on "simultaneous" ? 

3 - And lastly what is the result if the the sequence is not followed?  

3.5.2 Power-down Sequence

The AM3517/05 device proceeds with the power-down sequence shown below. The following steps give an example of the power-down sequence supported by the AM3517/05 device.

1. Reset AM3517/05 device

2. Stop all signals driven to AM3517/05 .

3. Option 1: Power down all domains simutaneously.

4. Option 2: If all domains cannot be powered down simultaneously, follow the below sequence:

(a) Power off all complex I/O domains

(b) Power off core domain (VDD_CORE)

(c) Power off all PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE)

(d) Power off all SRAM LDOs

(e) Power off all standard I/O domains (VDDS and VDDSHV)

  • 0
    TI__Genius 16690 points

    Russell Cumber said:
    1 - Are there any voltage ramp limitations during power down?  

    There is no voltage ramp limitation during power down sequence.

    Russell Cumber said:
    2 - In step 3, what is the tolerance on "simultaneous" ? 

    A strict requirement in the simultaneous power down sequencing is that the voltage difference between 1.8V power rails and 3.3 V power rails can't be more than 2 V. The voltage difference must be kept within < 2V during the power down sequence.

    Russell Cumber said:
    3 - And lastly what is the result if the the sequence is not followed?  

    It will affect long term reliability and could cause latch-up or ESD issue.