Power-down Sequence Clarification

Russell Cumber

Prodigy 100 points

Other Parts Discussed in Thread: AM3517

I could use some clarification on the following section of the user manual.

1 - Are there any voltage ramp limitations during power down?

2 - In step 3, what is the tolerance on "simultaneous" ?

3 - And lastly what is the result if the the sequence is not followed?

3.5.2 Power-down Sequence

The AM3517/05 device proceeds with the power-down sequence shown below. The following steps give an example of the power-down sequence supported by the AM3517/05 device.

1. Reset AM3517/05 device

2. Stop all signals driven to AM3517/05 .

3. Option 1: Power down all domains simutaneously.

4. Option 2: If all domains cannot be powered down simultaneously, follow the below sequence:

(a) Power off all complex I/O domains

(b) Power off core domain (VDD_CORE)

(c) Power off all PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE)

(d) Power off all SRAM LDOs

(e) Power off all standard I/O domains (VDDS and VDDSHV)

over 14 years ago

0 A4 K7 over 14 years ago

Intellectual 310 points

Logic PD released a new tool today that allows you to monitor the voltage rails during startup. Both the voltage and current can be monitored. Perhaps this will help you debug your issues.
There is an adapter required to connect to the PC available from this website: http://createnewstuff.webs.com/breakoutboardwattson.htm

The Logic PD software is available from here: http://www.logicpd.com/wattson

-A

Processors

Processors forum

Power-down Sequence Clarification

1. Reset AM3517/05 device

2. Stop all signals driven to AM3517/05 .

3. Option 1: Power down all domains simutaneously.

4. Option 2: If all domains cannot be powered down simultaneously, follow the below sequence:

(a) Power off all complex I/O domains

(b) Power off core domain (VDD_CORE)

(c) Power off all PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE)

(d) Power off all SRAM LDOs

(e) Power off all standard I/O domains (VDDS and VDDSHV)