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Can't get SGMII working on board (works on EVM)

Bryan Haack
Prodigy 80 points

 We are using the existing EVM board files to try to get functions working on a board we have with 4 C6678 DSPs. In our case, only one of the DSPs is connected to the MArvell 88E1111 PHY. We are connected to SGMII0 instead of SGMII1. The EVM uses a 100Mhz core clock and 312.5Mhz SERDES clock. Our board uses 156.25Mhz for both of these clocks. We believe we have the PLLs adjusted correctly to compensate for our clock rates, but we are still not able to get the SERDES link up. We set the MPY field for 16X as our clock is ½ the rate of the EVM and the EVM had this field set for 8X. Is there an updated user guide for the EMAC? The EVM has the rate field for the RX and TX configuration set to 10 hex and states this is set for quarter rate. The user guide says this field  should always be set to 01 hex, “Operating rate. Always write 01b to this register field. All other values are reserved.” We are also wondering if we need to adjust the EQ, SWING, or DEMPHASIS fields as these seem like they could vary from board to board. Additionally, there is a comment in the EVM code regarding a DV value that looks like it is a register value that could be set. We do not see this getting set anywhere, but it looks like several values were tried until the right one was found.


 I looked at the SGMII RX and TX lines and the voltage swing appears to be okay, but I’m unsure of the DC offset. I tried to take some measurements on the EVM, but since there is no silkscreen on the capacitors, I am not sure where the RX caps are for the SGMII. I did find the TX lines and the voltages are in line with what we see on our board. The RX on the PHY side has a single ended range of 1.16V to 1.53V. The DSP side is -67mV to 333mv. This doesn’t seem quite right, but I’m not sure what would be causing this since the lines are AC coupled. The 6678 datasheet states the SERDES should operate at 300mV to TBD. Has this been updated? If this needed to be adjusted, I’m not sure if it would need to be done on the PHY side or DSP side, but our PHY setup is the same as on the EVM. The output characteristics can be tweaked via register writes, but that would need to be done over MDIO and we don’t see any MDIO activity on the EVM.


 The issue appears to be that the SGMII interface is not autonegotiating correctly as that section of the code gets stuck in a loop.


 Any help on these issues would be appreciated.

  • 0
    TI__Intellectual 1880 points

    Bryan,

    I hope that the following information helps with your debug.

     

    You are correct that the RATE field for the TX and RX SERDES accepts values other than 2'b01. This is a mistake in the user guide, and it will be updated in the next release. The following correction will be made to the user guide for the SGMII_SERDES_CFGRX.RATE field:

    2'b00 - full rate, Two data samples taken per PLL output clock cycle (maintains rate)

    2'b01 - half rate, One data sample taken per PLL output clock cycle (reduces rate by 2)

    2'b10 - quarter rate, One data sample taken every 2 pll output clock cycles (reduces rate by 4)

    2'b11 - thirty-second rate, one data sample taken every 16 PLL output clock cycles (reduces rate by 32)

     

    The equation for determining the the values to use for ratescale and mpy goes a follows:

    refclk = linerate * ratescale / mpy

     

    You are setting your refclk to 156.25.

    Your linerate needs to be 1250 MHz for 1000 MHz operation.

    The ratescale goes as follows:

    Full,    SGMII_SERDES_CFGRX.RATE = 2'b00, ratescale = 0.5 

    Half,    SGMII_SERDES_CFGRX.RATE = 2'b01, ratescale = 1 

    Quarter, SGMII_SERDES_CFGRX.RATE = 2'b10, ratescale = 2 

    32nd,    SGMII_SERDES_CFGRX.RATE = 2'b11, ratescale = 16 

     

    There are several combinations of ratescale and mpy that you can use to setup the SERDES.

     

    If you want to use MPY = 16, then your ratescale needs to be 2. (156.25*16/1250 = 2). For a ratescale of 2, you should set your device to quarter rate: SGMII_SERDES_CFGRX.RATE = 2'b10.

     

    A few other combinations that I suggest that you try are:

    Set SGMII_SERDES_CFGPLL.MPY=8, SGMII_SERDES_CFGRX.RATE = 2'b01

    Set SGMII_SERDES_CFGPLL.MPY=4, SGMII_SERDES_CFGRX.RATE = 2'b00

     

    If this does not work, can you please provide me with a couple of details? 

    What are you using as the reference clock to the PASS PLL, and how are you setting up the PASS PLL?

    Are you able to communicate with the Marvell PHY using the MDIO, and get a link with the PHY?

    What value are you seeing in the STATUS register in the SGMII module (0x02090114)?

     

    Thanks,

    Derek

  • 0 in reply to Derek Brown
    Expert 1290 points

    Hi Derek,

     

    Thanks for the reply.  We have MPY=16, ratescale=2, and refclk=156.25.  However, we are still unable to fully bring up the PHY.  We have disabled the PASS configuration.

    To test, we are running the "client" demo that ships with the MCSDK beta 2 package.  The only changes we have made to the program are to the MPY configuration call (setting it to 16 instead of 8) and to the Init_SGMII() function that handles the way the MAC port number is handled (it now treats port 0 as the EVM treaded port 1, i.e. slave mode, autonegotiation, etc.).

    The program hangs waiting for the PHY to specify that the link is active ( sgmiiStatus.bIsLinkUp ).

  • 0 in reply to r_robotics
    Prodigy 160 points

    Hi

     

           I also encountered the same question, could you tell me how to solve this problem is? have the answer?