AM6412: DDR4 ODT termination

We are looking for IO Control A and IO Control B parameters.

Darshan, the DDR register configuration tool that you show will facilitate changing ODT values.  For read, ODT is changed on the processor side in IOControlA section.  It appears from the snapshot that you have chosen 48ohms already.  Use the generated output files on the right, and build the appropriate file into your code (check the README for specifics)

DDR4 devices do not allow read of MR registers.  This is achievable on LPDDR4 devices.

Regards,

James

Hi JJD,

The DDR register configuration tool is what we got online and settings shown are default settings store in the tool.

Along with ODT register, I might change many more registers. We have working configuration and don't want to change many other registers (like DRAM timing/ DRAM ODT). All I want is to change just the TI Controller side ODT register.

Thanks,
Darshan

Darshan, yes, this should be accomplished with the tool.  Your working configuration should have come from the tool (do you have that configuration?)  and any subsequent changes should be made there.  We don't support individually changing registers.

Regards,

James

Ok, let me try and update. Thanks!

Hi, 

We started with the general EVB software and we don't have sysconfig file. 

Can you share the sysconfig file for the generic EVB of AM64xx?

BTW, our s/w engineer generated 2 dtsi file keeping all the parameters same, except IO Control A - ODT for DQ/DQS/DM parameter.

IO Control A - ODT for DQ/DQS/DM parameter was changed between 40 and 48 ohms and dtsi file was generated.

Comparing the 2 DTSI file gave us the registers where Read ODT settings reside.

Looking at our current settings, ODT setting is 48ohms. But based on our measurements, I see "0" level settles to 360mV which can happen when ODT is 80ohms and not 48ohms. 

Something is disconnected. Please help.

Thanks,

Darshan

Hi Darshan, the default values in sysconfig for DDR4 will work for the AM64x EVM.  The configuration from the SDK that you started with may be slightly different, but that is just because the sysconfig tool has been updated since that configuration was generated.  I would start with the latest output from the sysconfig tool with the default DDR4 values, just to make sure you are at a same working starting point.  Then start making your adjustments.  

I agree that measurement doesn't seem correct.  Which signal(s) are you measuring?  Are you seeing any functional failures or just this voltage level disparity?

Regards,

James

.

We have moved much ahead with EVB settings. Will check with SW team if they are fine with moving to default sysconfig settings.

I am measuring DQ0 signal at the TI processor input. I should see "0" level swing close to 500mV instead I am seeing it close to 360mV.

Darshan, after measuring 360mV, can you take a register dump of the DDR subsystem registers?  You can do this in CCS with GEL script AM64 DDR Debug->Memory Debug->AM64_DDRSS_CTL_PI_PHY_RegDump run from R5 or A53.  If you don't have JTAG, let me know what you are using to initialize the DDR

Regards,

James