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Netra : TI816X . How to Use CodecEngine On A8 side to access VICP?

cc fan
Prodigy 120 points
Hi I have some trouble with the TI codec_engine_3_21_00_07, and hope I can get help from you SOC: TI816x (netra) contain 3 processors : one A8(cortex arm) and two M3 OS: A8 - linux M3 - Bios6 CodecEngine:3.21.00.07 App: We use the soc to develop a video system . capture Enc/Dec display the sdk demo configure the codec engine On M3 side, but I want to use codec engine On A8 linux side to use the VICP resources I want to know How to configure the codec engine ? Thanks all.
  • 0
    Expert 2030 points

    Codec Engine is for the 4th processor: DSP.  User code on m3 is not supported. M3 encode/decode can be done using openmax test bench in example-applications folder of the ezsdk.

     

    RV

  • 0 in reply to RV
    Prodigy 120 points
    To Rv: thank you . I looked into the source code of OMX Video Decoder component - OMX_vdec.c and I found the VISA API VIDDEC3_create and so on..And I think the component code is running on M3? The codecEngine is configured On M3 Local to access HDVICP resources? So , I hope to use VISA interface (like VIDDEC3_create..etc) on linux side . May be use Syslink to acess remote codec. Is there any method to do that?